If I want to use the FTDI Port B of the FPGA USB port as a serial to USB converter connected to a PC, I understand that I have to use signals BD0 (TXD), BD1 (RXD), BD2 (RTS) and BD3 (CTS) mapped to pins 46, 141, 140, 138 of the FPGA (for full hw handshake). Am I correct ? Is there any interference with the normal Papilio Loader programming ?
Regards, José Luis.