jlcollado

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About jlcollado

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  1. @Skip Thanks ! It's been a very satisfying experience building/programming to bring back these retrocomputers with 'new' FPGA technology. There is an updated version of the SD Card VHDL code that supports SDHC cards, thanks to Rienk Khoolstra and Neal Crook. When I get back home from my vacations next week I'll update my Upload.
  2. If I want to use the FTDI Port B of the FPGA USB port as a serial to USB converter connected to a PC, I understand that I have to use signals BD0 (TXD), BD1 (RXD), BD2 (RTS) and BD3 (CTS) mapped to pins 46, 141, 140, 138 of the FPGA (for full hw handshake). Am I correct ? Is there any interference with the normal Papilio Loader programming ? Regards, José Luis.
  3. Hi folks, I wanted to share with you my recently completed Project using the awesome Papilio Duo platform wit the Classic Computing Shield. It's a migration of Grant Searle's brillant work called MULTICOMP, consisting in a flexible FPGA based architecture for implementing old style 8 bit Retro-computers using Z80, 6502 & 6809 "Soft-core" CPU's. Below is the link to the Showcase article on this site. Cheers, José Luis.
  4. For an easy stratup, I'm adding an SD card image with all the CP/M disks initialization allready done, with lots of preloaded programs, ready to use (thanks to Oscar Vermeulen from obsolescence.wixsite.com for this nice compilation of CP/M classics !) Drives A: thru D: and Users 0 to 9 available in this image. [ Link to image file ] Enjoy ! Jose Luis.
  5. I've built the Z80 CP/M variant, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this: 1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, Z80, VGA, Serial, Keyboard, SD-Card) from the original design to fully use the Computing Shield peripherals and the DUO's SRAM (using and updated Computing Shield UCF file). 2. Converted the original 6 bit color VGA to 12 bit color interface. 2. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx's Core Generator's Block Memory instead of the original Altera Altsyncram IP. 3. Converted the internal double port Display & Attribute RAMs also to use the Core Generator's Block Memory instead of the original Altera Altsyncram IP. 4. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio's 32 MHz OSC instead of the original 50 MHz, but I ran into timing problems converting the many clock -dependant constants in the design. So I decided to generate a new 50 MHz clock using the DCM & PLL Wizard. Wherever possible I tried to maintain Grant's original VHDL & Z80 code, generating new signals and "wrapper" code to adapt to the different hardware. This way you can still refer to the original design as a rich learning experience, as every source code is available and well explained in Grant's website. The final outcome is a very usable and complete Z80 soft-core based machine, running the venerable Digital Research CP/M 2.2 OS. The modular design concept allows for extensive hacks and mods, even CP/M 3 and MP/M could be run (my next milestrone !). Hope you enjoy it ! I've attached some pictures of my working system and the full VHDL ISE 14.7 Project tree files, including an already generated "bit" file for transferring it to the Papilio Duo with the Computing Shield attached (default serial port baudrate is 9600, 8N1 no handshake).
  6. Sorry, found it, my mistake. Regards, JL.
  7. Sorry but this file is the same as the Papilio Duo; it does not provide the pinouts for the Computing Shield connectors (VGA, Serial, Keyboard, etc.). Cpould you please provide the correct file ? Thanks and regards, José Luis.
  8. Error 404 ! Please fix, as a user of the Papilio One this is a very important application file ! thanks and regards, JL
  9. Alex, thank you so much for your offer !!! Did you receive my PM ? Regards, Jose Luis.
  10. Can I upgrade by only changing the Spartan 3E chip, or is there another hw change to make ? Regards, JL.