Corey Kosak

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Corey Kosak last won the day on October 22 2013

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  1. Hi folks, I thought I'd share my third project with you all. I got sort of obsessed with the idea of driving the VGA protocol without any frame buffer memory backing the display (note 1) and I wanted to see how far I could get with such a design. I ended up with a cute little program that bounces a few geometric shapes around the screen and also does boundary and collision detection. There's a YouTube video here (http://youtu.be/ltEPILMaUMk) and the source code is here: https://github.com/kosak/PapilioPro-AnimatedShapes Feedback on the code is very welcome. I'm a newbie VHDL programmer and I find the language sort of frustrating so I sort of made up my own coding conventions and did some other hacks. I also agonized a lot about how modular such a design should be and how inter-module communication should work. In the process I've also generated a bunch of VHDL questions which I hope to post somewhere, if y'all don't mind. The first is hopefully an easy one: I used the IP Core generator to get a 25.175MHz pixel clock and it crapped out a huge number of files into my ipcore_dir. I'm sure most of those do not need to be checked into source control. Can you tell me which ones are supposed to be checked in? Thanks for looking at my demo! (note 1) mostly because I'm intimidated by the SDRAM :-)
  2. Hi folks, I'd like to show off my first Papilio Pro project. It's not much by anybody else's standards, but I was quite excited to get to this point after only a couple of days, starting from zero knowledge. Mike Field's tutorial was awesome! I hope that this is an appropriate use of this forum. I realize that others on the forum seem to be much more sophisticated. The project continuously increments a 16-bit counter, then renders that counter on the LED display. The project has three components: one that does the counter, one that multiplexes the counter onto the display, and one that translates 4-bit hex nibbles into 7-segment values suitable for display. I'm actually quite surprised that it worked without too much pain. I had to guess here and there. Here's a video: http://www.flickr.com/photos/15819666@N00/10388671913/ My .vhd and .ucf files are attached. I called the top-level file "Beef" because it was displaying 0xBEEF in the earlier stages of the design. I also had a couple of questions if you don't mind. 1 - I notice that the software spews out a huge number of files into my working directory. Is there a way to cleanly separate my source files from all these tool-generated intermediate files? An analogy in the C++ world is that I'd like to keep my .cc, .h, and Makefiles in a separate place from the .o and executable files. This makes for easy management with version control and also easy sharing (there's no point in checking in or sharing all these tool-generated intermediate files). What do other people do here? 2 - In a case statement (such as that in SevenSegMultiplexor.vhd) I tend to need a line like ``when others => ENABLES <= "XXXX";'' I was staring at the 9-valued logic page in Wikipedia and I couldn't decide whether I wanted "XXXX", "WWWW", "UUUU", or "----" here. I actually would have guessed "----" meaning `don't care` but XXXX seemed to work without complaint. Which is the most appropriate? 3 - I could have inlined HexTo7Seg inside SevenSegMultiplexor but I liked the way it looked as a separate component. Is this a reasonable thing to do? Any advice would be greatly appreciated. And thanks! I've had a fun weekend! View attachment: counter project.zip