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About offroad

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  1. Well, but you are looking at FPGA design from a fairly unusual viewpoint :-) Thinking pragmatically, an Artix-7 would make a new user's life considerably easier over Spartan 6 simply because it comes with Vivado instead of ISE. I don't think the user needs to know anything about the internal architecture - click the green arrow and out comes a bitstream. Of course this approach will hit some wall eventually, but at a surprisingly high level, possibly into the realm of VGA pixel clocks.
  2. Thanks, you're right. I checked my board, it's D alright.
  3. Hmmm... the old Papilios use the FT2232D USB chip, the newer ones (e.g. Papilio Pro) the FT2232H high speed variant. With a more recent board, uploads "should" be fast. I'm using high speed (30 MHz, clock divider 0) JTAG with the -H chip routinely. For xc3sprog, it may be enough to write cables.txt via command line option, then edit the clock rate. I think I've done that once and got upload times (but probably for a compressed bitstream) 200 ms or so.
  4. Hi, you could check Trenz TE0725 with Artix 7 up to -100 size. I once had a Microblaze on one of them (was replaced later in the design cycle) and it definitely utilized less than 1/3 of resources. You'll want the Digilent-licensed "XMOD-FTDI" adapter to use the debugger (no idea how hard it is to set up with multiple targets, there is one JTAG option USER1-4 in the MB config that might be relevant). There is a 1.8 V variant, most likely 3.3 V is the better choice. To put it into perspective, it's probably 2x...3x the price of a Papilio. With Vivado on Artix I think you have more microblaze configuration options than on Spartan with ISE. Note: I'm not aware of any ready-made solution to access the memory module on that board. For the Papilios there are soft memory controllers, and Pipistrelly can use the hardware core that's bonded out on the larger FPGA sizes. And, for Spartan 6 there is some community but I haven't found that yet for Artix...
  5. Nice that you got it working. Just make sure no one reads this as a recommended first-step response to a board that doesn't show on USB... My experience: I've thrown some of my own (boxed) FPGA designs across the lab and smashed them against hard surfaces under the pretense :-) of drop testing. Several dozens of units. While this led to mechanical design changes, I've never managed to break a crystal, or in fact anything electronic on a board. So I wouldn't be too worried about shock-sensitive crystals. To me, this seems a failure mode as likely as thousands of others.
  6. FYI: This is the FTDI board to rule them all: "-H" means high speed version, the MPSSE will clock up to 30 MHz and this works reliably with JTAG+Xilinx. You can get it from many vendors.The same exists for quad-channel FT4232H BTW, but I prefer the remaining pins as GPIO. It has proper protection circuitry on the USB port, which most other boards are lacking. I am using those in volume for industrial automation BTW.
  7. BTW, here is the official definition of drive strength, straight from the horse's mouth: "The drive strength of an I/O specifies how much current we can drive and sink while maintaining the minimum Voh and Vol levels." The bold part is the catch: it doesn't refer to the short circuit current.
  8. Hi, the outputs cannot be used as constant current source. Been there, done that, got the T-shirt and had to buy a new LED. If absolutely desperate, I'd use PWM: E.g. generate a 200 MHz clock and a counter that generates one pulse in 32 or so. With a short circuit current ~ 300 mA this should give no more than ~ 10 mA in average. But this is a hack in oh-so-many ways (among them: tune it to a radio station of your choice...)
  9. Hi, the very bright decimal points were indeed one "feature" of the resistor-less board. But best take a magnifying glass and look for the resistors, then you have peace of mind. I'd simply use a multimeter in diode mode on the headers to check the segments, or jumper wires to +3.3 V / GND (but don't do this without resistors or there will be 7-segment magic smoke).
  10. Hi, random guess: Is it possible that the UART pins are swapped? It seems unlikely, but undriven digital inputs can do this kind of crosscoupling voodoo.
  11. If it helps: there is no need for resistors. You can plug male-female jumper wires into the FPGA board on one side and a 15 pin VGA cable on the other (the diameter of the pin matches). I'm using this as a standard debug tool in 640x480 just HSYNC, VSYNC, GREEN (on/off) and GND. The voltage is slightly out-of-spec but the monitors I've tried with didn't object. I think you won't regret buying a scope. Another immensely useful and free tool is an "activity detector" where you trigger a counter using an unused input and put e.g. every 5th bit on a different LED. Then plug a wire into the input and probe as needed. You could try to fit a SUMP logic analyzer core into the design (disclaimer, never tried this myself. For me it works as advertised on a 2nd board). Edit and pay attention to your programming LED. It is possible that the FPGA resets for whatever reason (e.g. random short circuit on 3.3 V when you move the boards a certain way).
  12. Just wondering: Do you know the Microblaze debugger that comes with Web-edition Vivado? I've used the basic features (breakpoints, step, edit variables etc) on an Artix. It was surprisingly simple and usable without having read any manual.
  13. BTW if anybody is interested: I could dig up my 640x480 monochrome text adapter (40x20 char) that fits into a single 2kByte block ram. It's ugly as hell but excellent for debugging as one write port of DP ram can be used by the application at any clock without restrictions.
  14. Hi, did you check the voltage rating of the RAM? I think it's 5 V, won't work in a 3.3 V environment. The Papilio Duo might be able to do the job with its on-board SRAM, or Saanlima's Pepino.
  15. Stumbling over my old post, if someone is sent here by Google on a mission to reduce latency... The secret to achieving low latency with a UART is... don't use a UART. The 2232H chip, programmed through the DLL interface, can achieve physical roundtrip (!) times, e.g. send a byte via JTAG bypass through the FPGA and back in MPSSE mode, of slightly over 1/8 ms. If I extrapolate the 3.75 ms UART roundtrip time I achieved earlier... my boss wouldn't be happy :-)