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About joosteto

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  1. Thanks Magnus! Yes, the .vhd and .ucf files you provided do work. I do know papilio-prog uses a different bscan file, but somehow I couldn't find any other .vhd or .v files in the papilio-prog source code. I now see that the file you sent is actually present in the git repository (although the one from git looks like an older version), so I apologize. Thanks for the quick help!
  2. I'm trying to build the ./bscan_spi_xc6slx9.bit file from source, to program the flash on my Papilio Pro board. From the git source, the only .v or .vhdl source file for Spartan 6 is: ./xc3sprog/trunk/bscan_spi/bscan_s6_spi_isf_ext.v Is this the one I should use? Then for the User Constraints File, the only relevant one I can find is the generic one, The two files obviously don't match, so I from the .ucf file I removed everything except the FLASH_* lines. And in the .v file, I replaced all the MOSI/MISO lines with the FLASH_SI/SO etc lines, like: module top ( output wire FLASH_SI, //MOSI, output wire FLASH_CS, //CSB, output wire FLASH_CK, //DRCK1, input FLASH_SO //MISO ); (and all other places) The resulting .v & .ucf files do generate a bscan .bit file, but when I use that to program the flash, I get this: ./papilio-prog -f ../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit -b ~joostje/VHDL/bscan-Papilio/top.bit -v Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "/home/joostje/VHDL/bscan-Papilio/top.bit". DNA is 0xb9c95021930a5ffe Done. Programming time 547.0 ms Programming External Flash Memory with "../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 178 read 10 retries 8 Using the original bscan_spi_xc6slx9.bit does work: As for the reason why I want to build the source (apart from "I should be able to"), I'm using a modified Papilio board design with a Spartan XC6SLX16 (256 pin BGA), So I need to generate a new bitfile for that XC6SLX16. So, doesn anyone know where the .v or .vhdl source files (preferably with a .ucf file) are that can generate a .bit file for the Spartan 6 (Papilio Pro)? Papilio-Loader source was this morning cloned from here: (I've attached my modified .ucf and .v files, both renamed to .txt as the uploader didn't like my .ucf extention) Thanks, joost BPC3011-Papilio_Pro-general.txt bscan_s6_spi_isf_ext.txt
  3. Ah, I now see I papilio-prog uses the bscan from Java-GUI, not the ones from xc3sprog, so that was the reason programming failed for me. If anyone else encounters this problem, this works for me: From the Papilio-Loader/papilio-prog directory, this does work: sudo ./papilio-prog -v -f ~/VHDL/ClkTrig/design_top.bit -b ../Java-GUI/programmer/bscan_spi_xc3s500e.bit -sa -r As I showed above in my postings, using the bscan_spi_xc3s500e.bit from xc3sprog doesn't work, and gives the messages: Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. BTW, even now I cannot find documentation on what bitfile to use for xc3500e, at least not here Only by looking at the papilio-prog source I realised papilio-prog uses a different 'magic' code than xc3sprog, so the bscan binaries must be different. Thanks for the help!
  4. Thanks for verifying it! Could you write the parameters you gave papilio-prog to do it? For me, this works (not sending to flash): sudo ./papilio-prog -v -f ~/VHDL/ClkTrig/design_top.bit -sa but this doesn't: sudo ./papilio-prog -v -f ~/VHDL/ClkTrig/design_top.bit -b ../xc3sprog/trunk/bscan_spi/bscan_spi_xc3s500e_papilio.bit -sa -r and reports the error: Programming External Flash Memory with "/home/joostje/VHDL/ClkTrig/design_top.bit". Uknown Flash Manufacturer (0x00) However, I can program it the flash with the 'hacked' (as described above) xc3sprog, so it is at least somewhat functional. Maybe my computer is slower than yours, whatever.
  5. One more note: * I hacked xc3sprog to detect the location where the missing 2 bytes will occur, and to addd two zero bytes in the stream (see below) yeah, a really bad hack, but it does work * The 2 bytes before the 0x6c33 are 0x9a, 0x65, that happens to be half of the bit-reverse of the 'magic' 0x59, 0xa6, defined in progalgspiflash.cpp and bscan*.vhd -- is that a coincidence? So around the ProgAlgSPIFlash::program() function, this line: spi_xfer_user1(NULL,0,0,&AAIP_Cmd[0], 0, inAAImode ? 3 : 6); now has been replaced by: if(willfail){ uint8_t buf[6]; memcpy(buf, AAIP_Cmd, 6); buf[1]=buf[2]=0; printf("* * * * * prepending zero's! * * * * * \n"); spi_xfer_user1(NULL,0,0,buf, 0, inAAImode ? 3 : 6); } spi_xfer_user1(NULL,0,0,&AAIP_Cmd[0], 0, inAAImode ? 3 : 6); //If we see the 'magic', the next send will fail: willfail=(AAIP_Cmd[1]==0x59)&&(AAIP_Cmd[2]==0xa6); (and a declaration of the willfail variable). I know this is a bad hack, but maybe someone else now notices the real problem. Question: * Can anyone else with a Papilio One try the design_top.bit file I attached at the top of this thread with xc3sprog? I really would like to know if it is just my setup.
  6. Thanks for the suggestion. When I compile and run papilio-prog, I get this: $ sudo ./papilio-prog -v -f ~/VHDL/LEDTest/LEDtest.bit -b ../xc3sprog/trunk/bscan_spi/bscan_spi_xc3s500e_papilio.bit -sa -r Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E Uploading "../xc3sprog/trunk/bscan_spi/bscan_spi_xc3s500e_papilio.bit". Done. Programming time 444.9 ms Programming External Flash Memory with "/home/joostje/VHDL/LEDTest/LEDtest.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 148 read 8 retries 8 This seems similar to But `git pull` (repository: git:// reports that I'm up-to-date. How do I check the version of papilio-prog that I have (If I do indeed need the v2.3)? (The above command uses a .bit file that xc3sprog can send to the papilio flash without any problems)
  7. I'm trying to write my (Xilinx ISE generated) .bif file to the papilio flash, and xc3sprog gives this Verifying Failure (see below). It seems somehow 6c33 is inserted in the bitstream. After page 245 many more pages fail. Re-trying the same command will fail with the same errors at the same page. I can flash other .bit files, it really seems to be this bit file that is a problem (this .bit file is from a sligtly larger project, maybe it's the size?) The bitfile can be sent to the FPGA directly (without the -I and -R options to xc3sprog) ./xc3sprog -c papilio -I../bscan_spi/bscan_spi_xc3s500e_papilio.bit ~/VHDL/ClkTrig/design_top.bit -v -R [...] Verifying page 244/ 1109 at flash page 244 Verify failed at flash_page 245 read:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d577eebb0000000000000000ffff2f00adf0fc0787a5cec300000000cec393cc765687005bf39a650ef530225599000000000c0a0fa50000000000000000be96d8271b0050af000000000000000000000000000000000000000000000000 file:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d577eebb0000000000000000ffff2f00adf0fc0787a5cec300000000cec393cc765687005bf39a656c330ef530225599000000000c0a0fa50000000000000000be96d8271b0050af00000000000000000000000000000000000000000000 Attached is the design_top.bit file that causes the problem, and the full output of xs3sprog. I'm using the Papilio One; XC3SPROG © 2004-2011 xc3sprog project $Rev: 691 $ OS: Linux (retrieved from git 17th of april 2013) Ubuntu 13.04 Anyone know a fix? design_top.bit verify-failure.txt