cjameshuff

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About cjameshuff

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  1. This might be of interest as well: https://github.com/cjameshuff/pload Disclaimer: I've just got this working, it's not terribly well documented or tested, and it's basically the first substantial project I've done with VHDL. It does read, write, and erase the SPI flash on the Papilio One, though.
  2. On my Linux Mint machine, it takes 21 s to write and verify a 278 kB bit file, so there may be something strange there. There's two FTDI libraries, and IIRC papilio-prog can be compiled with either one. Try recompiling it with the other one?
  3. Unless another version showed up when I wasn't looking, it's Papilio Pro, and DRAM, not SRAM. I'd been intending to wire up a DRAM chip to my Papilio One, but parallel data/address busses are a pain to wire up by hand. I was going to do a board, but now I have a Papilio Pro. If you just need memory, easiest might probably be a SPI dataflash, just due to the number of address/data lines to hook up in the alternatives. That's not volatile, but while they exist, serial SRAMs are scarce and relatively expensive, and I didn't find any that large in a quick search (largest I saw was 1 Mbit, 128 KB). If you're worried about wear (and note that some are rated for 100000+ cycles), just get a huge one and spread your writes out.
  4. I've just done something similar with an old Epson EG2401 display. It doesn't really have enough pixels for Lena, and a single dual-port block RAM suffices as the frame buffer. I made a buffer board to produce 5V logic for the LCD (using 74AHC541s) and used a MAX232 to generate the needed negative voltage. I'd already done this with an AVR, and was able to get reasonably good grayscale by only setting lighter pixels for some fraction of updates. I might try that as my next step here. Avoiding flicker does require "overclocking" the display a good bit past what it was rated for, mine seems very tolerant of such abuse (I only started getting glitches when I gave it a 32 MHz pixel clock with the FPGA controller). Source code: https://github.com/cjameshuff/vhdlstuff/blob/master/sed11x0_lcd.vhd This post has been promoted to an article
  5. I've just done something similar with an old Epson EG2401 display. It doesn't really have enough pixels for Lena, and a single dual-port block RAM suffices as the frame buffer. I made a buffer board to produce 5V logic for the LCD (using 74AHC541s) and used a MAX232 to generate the needed negative voltage. I'd already done this with an AVR, and was able to get reasonably good grayscale by only setting lighter pixels for some fraction of updates. I might try that as my next step here. Avoiding flicker does require "overclocking" the display a good bit past what it was rated for, mine seems very tolerant of such abuse (I only started getting glitches when I gave it a 32 MHz pixel clock with the FPGA controller). Source code: https://github.com/cjameshuff/vhdlstuff/blob/master/sed11x0_lcd.vhd