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About james1095

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  • Birthday 03/04/1979

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  • Gender Male
  • Location Seattle, WA
  • Interests Engineering, electronics, mechanical tinkering, aviation, retro computing, retro gaming, hardware hacking

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  1. This has been discussed in the past but recently I came across a nice little 4:3 aspect ratio QVGA TFT which is very easy to use with just about any FPGA project that produces a roughly SD-TV resolution image, ie most early arcade games and 8 bit computers. This is the LQ035NC111, an older but still fairly widely available display which uses a parallel RGB-dotclock interface that does not require any type of initialization sequence to work, shown here running PacMan from fpgaarcade. These displays are nearly perfect for this application due to the 4:3 aspect ratio and resolution conveniently close to most classic arcade games, they're commonly used in those cheap backup camera monitors from China. The modifications to the code are very simple, all you need to do is feed the 6MHz ena_6 to the DCLK pin, reset_h to the reset pin and RGB/Hsync/Vsync to their respective pins then tie the unused RGB inputs to ground. The photo looks really washed out but in reality the display looks quite nice with good color and reasonable contrast. The only small hassle is that these displays have no built in backlight driver so you need a boost converter capable of producing about 20V and driving 10-20mA for the LED string. I lashed it all up with an ebay breakout board but eventually I'll make something more permanent. The plan is to scale down the plans and build some tiny desktop arcade cabinets but it could also be used to build a handheld or desktop version of virtually any game, console, computer or other application that fits in the FPGA and produces a video signal. If anyone hooks one of these up and has difficulty getting it going I'd be happy to help. arcade tft
  2. Well one of the big advantages of open source hardware is that anyone can build more of them any time they want provided the components are still available. I see two sides to the hardware situation. On one hand it's always nice to have options, but on the other hand the FPGA development community is so small as it is and every additional platform out there creates further fragmentation. In general I would say that it's a better use of resources to work on the collection of projects that run on the FPGAs rather than creating even more competing hardware platforms. An exception to this, and one that I think Gadget Factory could really excel at is producing peripheral modules to work with the FPGA boards already out there. The Papilio wings are the obvious place to start but it may make sense to expand to some of the various little Chinese dev boards that are out there. It would be great to see more widgets in wing format complete with some example HDL to make them do something out of the box.
  3. I think there is *some* value in the schematic based entry, for a total beginner it provides a way to make the FPGA or CPLD "do something" and helps to drive home the point that you are designing hardware rather than writing a program. It's not a bad idea to do a few simple projects using the schematic, but then move on to HDL as soon as you get beyond stuff like blinking LEDs.
  4. As far as web based stuff goes the UI looks nice, but it still doesn't solve the issue that I am away from reliable (or any) internet access just often enough that I don't want to rely on it for anything that I can run locally. If a proper desktop application is available I will always use it, web based stuff is a backup that is convenient when I'm not on my own PC.
  5. I haven't tried this yet but it looks like it should be straightforward to port it to any of the Papilio boards. http://forums.arcade-museum.com/showthread.php?t=364662
  6. There's another great book called Free Range VHDL, I found it to be tremendously helpful once I got started. What I did was read the whole book through from cover to cover without worrying too much about soaking it all in, then I went back and started going through the examples and referring to other sections as needed.
  7. I think for a beginner oriented board like the Papilio series a newer, larger, more powerful FPGA may be more of a curse than a benefit. Amongst my collection of FPGA boards I find that the two most powerful, a PrimeSense with Virtex5 and a DE2-115 with a large Cyclone IV hardly ever get used for anything. None of my designs come anywhere close to needing such a large FPGA and regardless of what I do with it, the larger more complex devices take longer to compile for, in some cases dramatically so. With so many soft core processors out there I've never even bothered to try the Microblaze or NIOS cores, I've just never had a reason. It would be nice if Xilinx would change the licensing terms for the ISE Webpack to match those of Vivado, all it would take is offering a different license file. Frankly I've never understood why they have any restrictions at all, just give away the fully featured software for personal use and have paid support subscriptions for commercial users like all the microcontroller manufactures. Give away the software for free because it sells hardware which is their core business. Aggressively court hobbyists and students because some of them go on to become engineers and they are likely to keep using the product lines they are familiar with. Anyway, back on topic. What the Papilio boards do lack is IO and memory. The Pro has SDRAM but that does not lend itself easily to retro hardware which is my primary interest. Block RAM within the FPGA is a scarce and precious resource and 95% of the time it's a lack of sufficient memory that prevents a design from fitting in a smaller FPGA. Having external SRAM and ROM or sufficient IO pins to add it opens the door to many more projects.
  8. The libraries are a fantastic aspect of the Arduino and the key thing that makes it a worthwhile if otherwise rather flawed platform. It took me a long time to warm up to Arduino but I love the way I can grab some widget and very often grab a library with example code to make it do something right away. It provides a great way to test the thing out and explore its capabilities right off the bat. I'd love to see a similar collection of HDL modules form, blocks of code that do the grunt work like initializing the device and communicating via whatever interface it uses and bring the controls out to sensible interfaces that can be tied into other modules in the top level file. Ideally these modules should be well commented, especially at the top level explaining what all the inputs and outputs do and what sort of signals they expect.
  9. I may be showing my age but I absolutely loathe nearly any kind of web based software. There are certain things it is convenient for, checking email when I'm away from my own PC with a proper desktop client, occasionally a simple tool, but for any kind of productivity software I find it frustrating. It's always slower, invariably I seem to have to do a lot of scrolling, it never seems to work equally well in all browsers, then for reasons I've never been able to fathom many browsers interpret the backspace key as navigate back to the previous page causing you to lose all the data. I'm forced to use a lot of web based crap at work and I never have taken to liking it. Especially these days when vastly powerful PCs with massive hard drives and gobs of RAM cost peanuts I'm baffled by the trend to return the the mainframe-dumb terminal paradigm. I guess what's old enough is new. That said, I suppose it doesn't really matter to me, I'm pretty content using ISE for my Papilio boards. I'd much rather spend any time I have writing code rather than learning a new tool. VHDL and Verilog are industry standards, code written in a standard language can be synthesized on any suitably large FPGA with minimal changes. With so few developers in the community it's essential to minimize fragmentation.
  10. I didn't take any pictures but it's pretty trivial to load it onto a Papilio Pro and fire it up. It just looks like Centipede, the only major issue it still has is the sound not working and I'm not sure why that is because I didn't mess with that part.
  11. This has more or less been my opinion for a while, DesignLab is a neat idea but IMHO it is a huge amount of work to create and maintain while in the end being a dead end that will serve as a crutch enabling people to avoid ever learning HDL and that will become a huge limiting factor down the road. I'm not going to try to tell you what to do but I think it would be great to focus on collecting a library of code a bit like OpenCores, processors, support chips, sound chips, and other interesting widgets that are tested working, and then attempt to clean them up so that they're somewhat consistent and well commented. One of my favorite FPGA projects is the Multicomp by Grant Searle because it is modular and provides a great tutorial on "wiring" up VHDL components into simple but functional computers. Then there is the larger issue that despite the efforts of many including myself, there seem to be very, very few hobbyist FPGA developers, especially the really talented ones who have developed entire projects. I've tried and largely failed to recruit nearly every technically minded person I know and just haven't succeeded in getting much interest and this frustrates me. Part of this is that FPGA development *is* difficult and there is a very steep learning curve but I think an even bigger obstacle is the perception that it's hard when in actuality putting together a project out of existing modules is not much harder than writing an Arduino program. There is a lot of fragmentation, a number of different FPGA platforms out there, each with their own community and largely the same collection of code, much of which has been circulating for years. Too many people who do create interesting new projects seem reluctant to share their code which is something I find baffling, why bother to create something and show it off if you're not willing to share it? Anyway I think we need more people involved, more basic tutorials, more Multicomp-like projects, think something like a kit where the main components are already coded and a tutorial is provided to write the code that glues it all together and results in something cool to play with. Maybe drum up some interest in local hackerspaces? A ~2 hour entry level presentation/class? A YouTube channel that presents FPGA exercises? Reverse engineering an existing FPGA project and explaining in detail what each section does? A tutorial to port projects from other FPGA platforms to the Papilio? I've learned a lot by porting various projects from Xilinx to Altera and vice versa. Something to get more people over the initial hump and writing some code, the more people we have contributing, the more interesting stuff there will be for everybody to draw from and contribute to. It's been far too quiet around here recently, I would love to see more people engaging.
  12. Perfect, thanks! So I had the second one right, the first one I had no idea but it makes sense now that I see it explained. The problem I've had with this sort of thing is trying to search for explanation I can't just google the line of code because the signal names are arbitrary. One of these days I should probably learn Verilog too but it's hard enough to be proficient in just one language without taking on a second one.
  13. Currently it's set up to use joysticks, the original Centipede hardware actually had joystick support but it was never used to my knowledge. Changing it to a trackball like the arcade cabinet should be trivial, the code is there, it's simply not "wired" up to the top level at the moment. The joystick input was just the easiest thing to use at this stage, once everything is working I'll hook up an arcade trackball I have, shouldn't be too hard to interface a PS/2 pointing device instead if one desired.
  14. Nobody is interested in Centipede? I got it 90% of the way there, the game is playable on the Papilio Pro, has anyone else had a go with it?
  15. After playing around with this a bit I've decided to translate it to VHDL so it's easier for me to work with. Most of it is pretty straightforward but a couple of the lines I'm not entirely sure what they do. Could one of the resident Verilog experts explain exactly what these two lines of code do? The second one I suspect is assigning cs <= '0' when internalSck is true but I'm not certain. idle <= &counter; if (internalSck) cs <= 1'b0;