Tb_

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About Tb_

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  1. http://dl.free.fr/k9Q7Q0PWo
  2. Kim following link will be available for 30 days: http://dl.free.fr/kRRdqxZUN
  3. I retrieve a previous download of sd_card_writer-17Feb2013.7z, it will be available for at least 30 days http://dl.free.fr/kOHFvTECK Thomas
  4. You probably configure the pin "tx" as an output and PULLUP option doesn't have sense in this context. By googleing : http://forums.xilinx.com/t5/Spartan-Family-FPGAs/PULLUP-on-an-active-net/td-p/143378 Thomas
  5. Project update I finally manage to add drum. Actually it read sample from the SD card. The current design is limited to one drum sound at the time. But I have in mind to enhance the system and be able to reproduce 4 drum sound in the same time in addition to the other sound ( up to 252 ). Even if I rework the design it is not yet timing net. More work on timing exception is required. I record a new video of the same midi song unfortunately I didn't improve my record sound system so the sound of the video is still very low and bass drum is quite difficult to heard... http://youtu.be/XX9kjhRqEsM Thomas
  6. I spend several hour on avalanche implementation too. But the absence of "on the self working example" stop me. Do you mean "interrupt reentrance is not necessarily a problem" ? Not interrested by windows toolchain. I manage to build mine. But it's a pain : no documentation. One build script in zpu db refer to '-phi' switch on zpu-elf-gcc : which option are relevant of the platform and which one are relevant of the core ? Only way to understand what it does is to dig into zpu gcc fork ... The 64 bits toolchain version only compile with a 'magic' no documented... No tutorial on how it would be possible to add a dedicated intruction in the compile toolchain, even in an asm section would be enough. All this thing make that i never figure have fun with zpu cpu, because i's too difficult to use for me. I think with at least on good tutorial. With sometime basic things explain : link script, uart integration in a bootcode/romcode and the role of the various compiler switch could reduce the gap and make this cpu core more popular.
  7. Excellent piece of code. This example make the integration of this CPU into an existing design quite simple .Too bad this core do not have interrupt support. Need to have a trial later...
  8. Not sure to understand all. I neither don't know if all logic analyser are working the same way. By using this kind of technique you cannot guarantee to record a known number of sample at a specific sample rate. Then you can't guarantee record for a minimum time. Because you have a dependency on the data observed. It can be any suite of binary symbol. The compression that reduce the number of symbol is interesting to send data through a PC in a reduced time. Fastest we can send data to host system and fastest we can reuse the local memory without loosing data. Also you can take 'snapshot' with an accurate and known number of sample at the maximal sampling rate. Also such system is probably more scalable. More money you have, more local memory you put on the system and more sample you can have in the 'snapshot' to increase the minimal record period. If i had to build to a logic analyser ( i don't know how are working other project). I would : Sample data and put them in a local memory. Send data from local memory to an host system to be display. The sample rate would be configurable, the number of channel to observe would be configurable. 1,2,4,8,16,32 ... in a first time. Ideally the upload link will have enough bandwidth to send all data from the local memory before the lost of data. Compression could be used here : it statistically increase the bandwidth, but you can also expect save power (off chip communication are more expensive in power than in chip communication) by transmitting less data. My 2c thought.
  9. I drive a spi clock of a SDCard at 48Mhz with this constraint in my Papilio One 500k project and a micro sdCard wing: NET CS LOC = "P35" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ; #Have you try a measure with a disconnected load ? What is exactly your load ? If you try to clock a micro-controller by this way, you may check the input datasheet of the mcu. Sometime such device require specific fuse setting to work with different oscillator technology. Thomas
  10. Check Table 1 in the documentation sum up ressource of the chip chip. http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf The HW description (the vhdl or verilog code) take too many ressource : The tool was not able to find the ressource to map your HW description on the HW ressource available. In your case it seems that you request a so big memory that the dedicated memory ressource in the fpga Block RAM (BRAM) wasn't enough. So the tool try to complete doing the memory with remaining flipflop ressources. But it failed claiming the lack of ressource. You can see in the Table 1 of the documentation that by choosing a bigger spartan6 fpga at some point the mapping would pass.
  11. About the pitaya, low sampling rate ? You should have missread. If you refere to the 125MS/s it is the sample limite of the ADC, i think it is quite honorable. As an logic analyser you can expect better performance than the dsl... because of the possibility of the HW provided (memory chip, ethernet ...) But yes actually they don't have adaptation board to probe -30/30V logical signals. And the logical analysier application seems not to be out-of-the-box features.
  12. There was several month ago a similar project on kickstarter : http://www.kickstarter.com/projects/652945597/red-pitaya-open-instruments-for-everyone Now the kickstarter compain is over but you can still buy one on their website : http://www.redpitaya.com/
  13. Hi I realize that i didn't post video update since a long time ago !!! http://www.youtube.com/watch?v=YadhN8LuyPg The sound is very low, because my speaker are quite away from my camera. Also it is the same midi file play used in the first demo but the design have completely change. The design still produce sound at 48Khz and is drive by midi protocol. I also implement pitchbend, aftertouch. Note off feedback. I pass the design at 96Mhz to avoid clock domain crossing between the uart and the synthesizer core. But today I am not sure it was a good idea. dummy because I run into timing not met issues : MULT18X18SIO seems to have propagation delay not in line with a clock at 96Mhz, so i change all my multiplier by core generate pipelined instance. So the design use more resources with no gain in feature... The benefice are that now i have enough cycle to loop the 256 row of my RAM16 and play 256 sounds at the sample time. While at 32Mhz i was limited to about 160 and i can avoid clock domain crossing (In a previous version the uart was working at 96Mhz but the synthesizer core run only at 32Mhz) Also if i wish to port on a spartan6, I can probably review this part to have a better usage of the fpga resources. If someone have a working example on how to setup a multi-cycle path constraint i am interest to learn : all my attempt failed to setup the constraint. Next step ... add the drum channel Thomas
  14. To compile zpu gcc tool chain available here http://repo.or.cz/w/zpugcc.git on a 64bit native linux workstation, the build.sh script need to be modify. Otherwise one of zpu tools we just compile and we use to build the toolchain will crash. binutils need to be compile with the additional following flags in CFLAGS variable: -DFORTIFY_SOURCE=0I use this tips on previous release of Ubuntu and didn't test it with the latest. Thomas
  15. Excellent ! I realized that I play this game on a PC i486 with no more that 640KB of memory.