hamster

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  1. That is like designing a rally car and asking if for best perfomance you should use racing slicks.... Let your engineers use whichever tool works for them - but it won't be C++!
  2. WIth 100 boards you won't be at the point where the engineering costs for your own PCBs start making sense over an off-the-shelf board, unless you have other constraints that make it very important to you. If a off-the-shelf costs $1,500, it might have a build cost of about $500 per board, so you only get $100,000 for board development and tested before it isn't worth it financially, and that doesn't include any allowance for the risks and the development time. Given that you could pay a little more and get some fully-featured dev boards on your desk tomorrow that people can work with straight away, verses a complex PCB development, including the associated risk and expenses it seems a no-brainier. You always have the option of designing a custom board once things are up and running and your requirements have been are completely understood. I would think that it is a very limited skills pool - FPGA/ASIC, low latency designs, high speed comms, most likely gigabit networking , tcp/ip protocols, the understanding of the on-the-wire trading protocols, and then implementing HFT algorithms. The pool of people would be very small - about the same size as a niche medical specialist (e.g. in the same order as Orthopedic surgeons who specialize in jaw reconstructions). Defiantly not main-stream skills.
  3. Hi oritemis.frc, I can give you an none-answer. We don't really have enough specs to give you a sensible answer. Say you wanted the top level of performance the entry price is pretty steep. If you wanted to accept multiple 10 Gbps fibers the hardware alone will cost something like $10k per instance. (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1328&Prod=NETFPGA-10G-SUME). If you only need multiple Gigabit interfaces the hardware is about $1.5k per board.. Tools to develop the application will cost $3k+ per year per seat. Any IP you license will also cost, like a wounded bull - for example a SATA IP block costs $20k per design. H/W cost is only a small bit. Engineering time will cost about $100k p.a. for an average VHDL engineer (see http://www.payscale.com/research/US/Skill=VHDL/Salary).Maybe $1k a day for a contractor. It would need a small team outside of the developers of main trading algorithm. - Software - embedded Linux will most likely be in there somewhere - A networking protocol engineer. - Programmable logic - maybe three engineers, or one really enthusiastic one. - Testing / Verification (e.g. making dummy feeds, testing benchmarking and so on. - Ongoing support. If you wanted to build custom boards you will need a high speed design engineer or two, and maybe $100k (if not more) for prototypes Development time frame really depends on system complexity - maybe 4 weeks, maybe 6 months. So as a rough budget. - hardware and setup for 5 engineers - maybe $100k. - Development resource (5 engineers for 6 months) - $8k per week per month per engineer = $240k - Office space, expenses, travel... - Contingency Call it $400k, on the back of an envelope, without actually knowning what you want to do.
  4. Make sure you have software flow control turned off on the pprt , or you will lose all you XON/XOFF characters. (\x11 and \x13 IIRC) Mike
  5. An old trick is you can clock a BRAM with "not clk" and the result of a lookup is ready before the next rising clock edge... However your designs Fmax might halve so it isn't suited for high performance designs.
  6. Once you get it gojng, rather than using a sine wave, why not try a GPS gold code? ( or something similar to one) It is a pseudo random bit stream that is quite long. When you correlate with an external signal you can get a really precise phase lock. This time to phase lock is what gives the long time to first fix of a GPS as it trys all the different alignments, but once locked it is very solid, even though the power levels of the signal is well below the noise floor and mixed up with all the other GPS birds. By having g a real time clock on the GPS the time to first fix is improved as the GPS knows where to start hunting. Also, I believe that most GPS units have a one bit DAC, so maybe a bandpass filter and to compare against the long term average is all you need?
  7. If you want to listen to an hour's banter about FPGAs, have a listen to this week's Amp Hour podcast. http://www.theamphour.com/237-an-interview-with-joe-and-mark-garrison-subtly-spelling-sayleeay/ It's a great interview with the guys behind the Saleae Logic Analysers.
  8. Hi, Somebody was after a way to send the input state of pins through to a host/PC for logging, so I knocked something up from them. http://hamsterworks.co.nz/mediawiki/index.php/Log_Pins It logs 11 pins as an ASCII string of ones and zeros, followed by a NL and CR, at 9600 baud on the virtual serial port. It only sends an update when the state of the input changes. Somebody might also be able to make use of it as a debugging interface...
  9. You may also want to break it down into smaller chunks, that you can put together into a working project. First start with turning on some LEDs, then.... a: Can you receive a single byte from the PC and display it on some LEDs? b: Can you generate a VGA test picture? c: Can you make a memory and play back a pattern onto LEDs? Then you can build a+b: Can you store bytes from the PC into a memory? b+c: Can you display a picture from memory? Then finally a+b+c: Taking data from the host, storing it in memory, and displaying it on the screen.
  10. If you have an passing interest in DSP or Software defined radio, then you simply have to watch this talk. It starts off pretty weak for a minute or so , but once the presenter gets going...
  11. GBs might be expecting a bit much. Here's an example part for you http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en559112 It has some funny 2-data-pin DDR mode, where you can get 10MB/s out of it. Not too shabby.
  12. Possibly? Yes. Practical? No. The speed of signals needed to operate a SDRAM chip property make this impractical. If you were to run you serial interface at 100MHz, and used ram with a 16 bit data bus the SDRAM chip would be clocked at about 6MHz. There are however static RAM chips with a serial interface that could be used, that require only three or four wires.
  13. You can do this - http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/using-just-the-switches-and-leds-on-the-logicst-r56 - and then you have 16 spare I/O pins where you can connect up more switches and LEDs using jumper wires (or Button wings).
  14. I've been thinking about this while mowing the lawns. The output of the piezo will have really high impedance, as is the ADC's input impedance. You might just get away with this (ignore the part names, ADC inputs are on the right): The Rs should be around quite high value - maybe 1M or above, and the diodes are to clamp the input just in case the input goes outside of the power supply range. Just try it without the low-pass filter cap first, and then experiment to find a suitable value - it should be around 0.47n or so to get a -3db filter of around 600Hz or so, assuming you use 1M ohm and the piezo output impedance is higher than than. Oh, and because of the high impedance, using an oscilloscope to watch what is going on will not give accurate readings. EDIT: The ADC's AC input impedance is about 100 ohms, so maybe some sort of buffer will be needed, esp for high sample rates.
  15. The ADC is 0-5v IIRC so if you use a rail to rail op-amp powered by 5v then there is no way that it could exceed the input range. One thing I just thought of is that the low pass filter is drawn to use a. Opamp with a +/- ?V supply, not 5v / 0V. I will sketch something up later tonight