alvieboy

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Everything posted by alvieboy

  1. I fixed paths (not yet on master) and generated a ZIP export file. Should work... not sure - fails on my side with: INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Care to try ? Your luck may vary... Alvie ZPUino_Papilio_One_250K_V2_blackbox_dist.zip
  2. I need to update that project file... I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around. Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though). Alvie
  3. Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly. Alvie
  4. Can you try swapping TXD/RXD in the UCF file ? I recall we had some "misunderstanding" regarding the TX/RX direction. That was a long time ago, though. Alvie
  5. Does your board have a "DONE" LED or pin so you can check if the FPGA starts ? Are FTDI/Serial connections the same as in original ? Why does your FPGA have a different ID code ?
  6. This one is still odd. Never saw it. Have you tried a different USB port? Best, Alvie
  7. Don't think it would fit any of the Papilio boards. Perhaps the big Pipistrello, have a chat with Magnus ( @mkarlsson ), he should know better than I do (and he uses Microblaze often). Alvie
  8. My Wii Chuck is a Nintendo original and worked with the posted settings, I may need to try your changes so se if it still works. Thanks a lot for testing this and finding a fix! Alvie
  9. More interested in the setup sequence. If you can capture that one it should shed some light. I suspect SDA is high-tied to VCC, hence the readings and the I2C ack.
  10. This seems to imply your Wii chucks are not properly powered?. I used a small adaptor back when I wrote the support code, and played with it for a whole maker faire (many people did). Do you have any digital scope so we can look at the signals ? Alvie
  11. GF does not support Zynq at the moment, nor Linux interfacing. But my 2 cents: 1 - flush the write to the GPIO control port. 2 - If you really need control over all lines, write a Linux Kernel Driver for it. Also check documentation for that "modbus" library you are using. Alvie
  12. Thanks for your reply, Luís. Yes, I am from Coimbra, but don't go to Lisbon that often (except to fly abroad, and that's more often that I'd wished). Still one question: how do you model sync vs. async resets ? Rather easy in low-level HDL languages, but hard to do even in SystemC (I heard newer versions do support it, but it's an ugly hack in my opinion). Alvie
  13. It may be possible with an USB3300 transceiver. I have a couple, but unfortunately had no time to put those to work. I may need to in a recent future, I'll let you know. Alvie
  14. I read one of your PDF files, and to be honest I have much more questions now than I had before, like: - How do you model different clock domains ? - How do you integrate with hard-IP blocks ? - How do you model multi-cycle operations, like a 5-pipeline multiplier ? If you happen to come by Coimbra you may explain me these in more detail Alvie
  15. Thanks for sharing. I still have to ship your stuff, will do so during this week. Also quite busy over here, but definitely have no connectivity issues I will try your design later, but more interested in the HDL design than in the demo. There's been quite some hype around RISC-V, but to be honest I believe it won't live longer - there are some issues with ISA, and some extensions may not play well with others. Also, MIPS is for sale AFAIK, if they drop the patents it may well be a more serious contender to ARM (I think at least Cavium may have some interest in buying MIPS from Imagination - and Imagination is eager to sell everything due to recent contract changes with Apple) Alvie
  16. it's probably better just to stream it using a serial port at 3Mbit/s. The audio DAC relies on the speaker themselves (their inductance) to perform a low-pass filter, in both Sigma-Delta and PWM outputs. What you hear is probably switching noise and some aliasing. Alternative is for you to design such an analogue filter. It can be technically possible to send that data over USB using a simple transceiver and isochronous transfers, but we have not done it before. Alvie
  17. Synchronous resets are not an issue. Reseting the clock generator is General rule is: - If you have a single clock on your system, make sure the reset signal is deasserted at least one clock cycle after your clocking is stable. Do not deassert it if you use a DCM/PLL until it locks. Do not reset DCM/PLL unless you absolutely need to. - For multiple clocks its a bit more tricky. You will need a reset for each of your clock domains. Here async reset for the reset itself may prove useful - assert resets asynchronously, but deassert them synchronously for each of your clock domains. May not be enough, though. Alvie
  18. You can try using ZPUino itself to perform the SPI programming. Let me know if you need some pointers on how to do it. Contact me at alvieboy@alvie.com Alvaro
  19. dcachev2_zpuino_preliminar.tar.gz

    Version 2.0.0

    25 downloads

    Preliminary ZPUino dcache (v2)
  20. Implementing a IWF cache (Important Word First) is quite complex. I did it for xThundercore (which is another CPU I am developing), but ended up quite big, and to be honest I did not see any spectacular performance improvement. One technique (which is simple, but may require compiler awareness) is to assume all forward branches to be a miss, and all backward branches to be a hit. I'll send you my dcache by private message (and the write buffer). Alvie
  21. Another question - note that I have had not much time to look at your implementation - why are you snooping the data bus cyc in the instruction cache (I assume it's your change, has a TH comment on it) ? Alvie
  22. Not if you use the embedded multipliers. Those are slow (never managed to get a 32x32 to work above ~105MHz or so). I have a data cache I wrote for ZPUino (not published, it's a two-way associative). Let me know if you want to take a look. Regarding bitfiles: how you program the design afterwards - or do you have to embed the code inside the bitfile ? We can try porting the ZPUino bootloader for your new platform, should be pretty much trivial. Alvie
  23. Do you have clang+llvm working for the platform ? Last time I looked it seemed like work in progress. Or do they use gcc ? What's the current clock rate for the system ? Can it go past 50Mhz ? Alvie
  24. I have powered ESP8266 using PPro rails just fine, even when overclocked. Just make sure you have a nice caps on ESP supply to support the high current bursts. On another note: I have ESP8266 wings ready, in case you want them. I can sell you the PCBs for USD1.5 each, plus shipping. Or I can share design with you if you want to build them yourself. Alvie
  25. Excellent. Now, we should document that somewhere... just unsure where. The code size different is substantial I believe, even if you don't actually use writes. Alvie