alvieboy

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Everything posted by alvieboy

  1. Actually, down to almost 1ns with our Spartan6 devices (that's the speed limit for serdes). But will be hard to propagate an almost-1GHz signal without a differential output and proper routing and layout. 1uS is just piece of cake. Anyway, rojhann, can you give us some pointers on how this output needs to be generated ?
  2. Only one thing missing: you need interrupts ? Will be hard to figure out where the interrupt came from (you know it's from the HUB, not necessarly from which device) Alvie
  3. Not really. I actually have been thinking about this HUB thing for some time, so it's basically already designed in my head, just needs implementation.
  4. Let me discuss this with Jack first, because it requires changing libraries to support the new HUB functions.
  5. One of the slots is used internally, so you only be able to access nine of them. So total number of avalable slots is 15. One option is to create a "HUB" that will get you 15 more slots. Would that work for you ?
  6. Simulation is always tricky, because you don't want the real life behaviour - for example, before loading the sketch from flash to RAM the bootloader waits for one second. This one second, if simulated, will take *ages*. So, for SDRAM/sketch, we use another approach, which is a different bootloader that jumps right to SDRAM @0, after enabling it. for SDRAM, you'll need a properly generated .srec file. Do you have any "trace.txt" that I can look at so to see what is preventing your simulation from running ?
  7. alvieboy

    I2C

    Hi, are your pins at logic '1' or '0' ? Do you have external pullups ? No need, it will detect the slot (you should see that when you start your sketch). If I recall well, it's how I2C handles read vs. writes (direction). See "I2C Device Addressing" here: http://www.robot-electronics.co.uk/acatalog/I2C_Tutorial.html
  8. @Tom: cost ? I may get my hands on one of those. Then I may be able to use parallella.
  9. It has a little help from a small, cheap CPLD (not many GPIO on the module), but otherwise yes, ESP8266 is driving everything. You can buy ESP8266 with ceramic antenna for about $2.5 each, in small quantities. Google for ESP-07. http://www.aliexpress.com/item/10pcs-ESP8266-serial-WIFI-model-ESP-07-Authenticity-Guaranteed-WIFI-module/32264981572.html
  10. You can take a look at my "initial" implementation for ESP8266, if you want. https://github.com/alvieboy/iotpanel/tree/master/firmware/esp8266/user It's basic right now. I'll improve design in next few weeks, so stay tuned.
  11. Ok... all transmission-only ? That should be fairly easy for transmission.
  12. Honestly... I have a Parallella. A super $99 FPGA/CPU. Never used it, and it's so damn hard to use it, and power consumption is so high I will probably just sell it. Cheaper chips and designs will be, like james1095 says, popping up daily. That does not mean that they are actually useable (I am currently struggling with ESP8266, due to lack of documentation). Although C.H.I.P. is an Allwinner ARM, and quite well supported in Linux.
  13. Yes, it is. You can use a "hub" to demultiplex one of the existing slots into, let's say, 1-to-8. However, current software is not aware of this. This is actually somehting I have discussed earlier with Jack. Do you need this in a short term ?
  14. He should have seen 2 serial ports. Perhaps wrong device ? Or driver issues.
  15. Please, send me an email so I won't forget this. I've most of those libs/apps scattered around my repos.
  16. Peripherals are the most standard way, although you can indeed use some "undefined" instructions in CPU. Note that with ZPU it will be very hard to use those instructions. GCC is tricky.
  17. One thing you can use is the RTL viewer that comes with ISE. It will give you some insight about how the synthesizer understood your "code". The technology viewer, however, will have everything mapped into LUT's and it's rather hard to understand how mapping was done. Alvie
  18. As I told you, I am able to stream raw audio @3MBit/s to ZPUino, play it, and no drops/errors. Full stream is 44100Hz*16bit*2 = 1.411200Mbit/s, and with some overhead (I use HDLC framing). ZPUino has a 2MByte receive buffer, as long as you do not exceed that, you're OK. I can share that code with you, but note that it uses my SerPro library, and for PC only QT and GLIB versions are available (not Java nor Python). Alvie
  19. ZPU is a stack processor, and stack processors are slow One thing they are bad at is branching, because it can never be predicted (it will be a word in stack, but you don't know which until you execute). Also bad at reloading the stack pointer. Another thing is they are bad for normal compliler integration, which do expect registers to exist (we emulate this behaviour by placing vregs in stack offsets). Adding "1" to a variable (which needs to be in stack) requires quite a few ops: loadsp [variable offset]im 1addstoresp [variable offset]In most register-based architectures, if your variable is a register, it takes a single instruction. Some other also allow adding to a memory location directly. Alvie
  20. Yes, no functional difference at all. However, if you do want to use "counterNext" more than once, it will tell synthesis tool that you want only one adder. Although it may not follow the advice. Not always true. Actually, I find the opposite much more readable and understanding, if you follow some rules/conventions. What I often do is this: -- Inputssignal ina, inb: std_logic;-- outputssignal outa, outb: std_logic;type sync_elements_type is record a: std_logic; b: std_logic;end record;signal r: sync_elements_type;process( clk, r, ina, inb ) variable w: sync_elements_type;begin w := r; -- copy regs into variable if ina=1 then w.a := '1'; -- Synchronous. outa <= '0'; -- Asynchronous outb <= '1'; elsif inb='1' then w.b :='1'; -- Synchronous. outb <= '0'; -- Asynchronous. outa <= '1'; else outa <= '1'; outb <= '1'; end if; if rising_edge(clk) then r <= w; -- Update synchronous elements. end if;end process;Alvie [Edit: it posted before I finished]
  21. Well, most designs use ZPUino Extreme Core, which is used by 1.0 and 2.0. FMUL16 is a quite dedicaded instruction, which helps if you do fixed-point 16.16, but needs to be instantiated in asm (and cannot be done from within "C" due to how GCC interacts with ZPU). FMUL16 behaves as: uint32_t fmul16(uint32_t lhs, uint32_t rhs){ uint64_t result = (uint64_t)lhs * (uint64_t)rhs; return result >> 16;}Quite useful for some DSP functions (like FFT).
  22. Lukas: you're losing data, because you don't read from serial port fast enough, and usually serial port buffers/FIFOs are small. LM32 is not to blame here. I suggest: * use a thread, with a simple read from serial port, which posts to a memory queue. * another thread reads from there, processes, and outputs. I can help you with that, if you need. Objective is to let read() get data from serial port as much as possible, and defer processing of data.
  23. Are you sure ? Note that there's a strict procedure to put SD cards in SPI mode (and AFAIK it's a mandatory mode), but returning to SD mode will require a power cycle. From SD Physical Layer spec: 7.2.1 Mode Selection and InitializationThe SD Card is powered up in the SD mode. It will enter SPI mode if the CS signal is asserted(negative) during the reception of the reset command (CMD0). If the card recognizes that the SD modeis required it will not respond to the command and remain in the SD mode. If SPI mode is required, thecard will switch to SPI and respond with the SPI mode R1 response.The only way to return to the SD mode is by entering the power cycle. In SPI mode, the SD Cardprotocol state machine in SD mode is not observed. All the SD Card commands supported in SPI modeare always available.I don't make a sense of "if SD mode is required". I assume it's a CMD0 argument. Also, make sure that before using card, you send at least 74 clock cycles with data=1 and card de-selected (CS=1). Alvie
  24. Ideally the synthesis will infer most of that for you, except on a few cases. The most relevant one is when you have an FF which drives an IO pin, and whose output feeds back to the FPGA logic. When this happens, it's not possible to place the FF in the IO Block directly. One option is to replicate the FF, and indeed if you do force the FF to be in an IOB, it will get replicated: Example: Unit <papilio_pro_top> processed.Replicating register sram_inst/ctrl/r_address_11 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_10 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_9 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_8 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_7 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_6 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_5 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_4 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_3 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_2 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_1 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_0 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_bank_1 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_bank_0 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd8 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd7 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd9 to handle IOB=TRUE attributeNow, for clocks: There are two main routing infrastructures inside FPGA. One is a general-purpose, used for data, and another is a fast one, used for clock. The latter does not allow a clock signal to propagate but to clock inputs in the CLBs. Also, not all input pins can drive the IBUFG which feed to the clock routing (or PLL/DCM which will then distribute clock accordingly). For clocks, you really want to instantiate the BUFG. If you use DCM and PLL with feedback, you do want to have a BUFG in the feedback loop. Most of other cases, assumung you have "add IO buffers" selected in the synthesis options, will work correctly. Alvie
  25. I wrote the application for hin to test. If a 0x00 is received it will be written to a file. Alvie