alvieboy

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About alvieboy

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  1. You can try using ZPUino itself to perform the SPI programming. Let me know if you need some pointers on how to do it. Contact me at alvieboy@alvie.com Alvaro
  2. dcachev2_zpuino_preliminar.tar.gz

    Version 2.0.0

    5 downloads

    Preliminary ZPUino dcache (v2)
  3. Implementing a IWF cache (Important Word First) is quite complex. I did it for xThundercore (which is another CPU I am developing), but ended up quite big, and to be honest I did not see any spectacular performance improvement. One technique (which is simple, but may require compiler awareness) is to assume all forward branches to be a miss, and all backward branches to be a hit. I'll send you my dcache by private message (and the write buffer). Alvie
  4. Another question - note that I have had not much time to look at your implementation - why are you snooping the data bus cyc in the instruction cache (I assume it's your change, has a TH comment on it) ? Alvie
  5. Not if you use the embedded multipliers. Those are slow (never managed to get a 32x32 to work above ~105MHz or so). I have a data cache I wrote for ZPUino (not published, it's a two-way associative). Let me know if you want to take a look. Regarding bitfiles: how you program the design afterwards - or do you have to embed the code inside the bitfile ? We can try porting the ZPUino bootloader for your new platform, should be pretty much trivial. Alvie
  6. Do you have clang+llvm working for the platform ? Last time I looked it seemed like work in progress. Or do they use gcc ? What's the current clock rate for the system ? Can it go past 50Mhz ? Alvie
  7. I have powered ESP8266 using PPro rails just fine, even when overclocked. Just make sure you have a nice caps on ESP supply to support the high current bursts. On another note: I have ESP8266 wings ready, in case you want them. I can sell you the PCBs for USD1.5 each, plus shipping. Or I can share design with you if you want to build them yourself. Alvie
  8. Excellent. Now, we should document that somewhere... just unsure where. The code size different is substantial I believe, even if you don't actually use writes. Alvie
  9. I assume you're using the SD library. If so, try creating a file named "config.h" in your sketch folder, and add the following line: #define SD_WRITE_SUPPORT 1 That should enable write support. Sorry this is not documented anywhere. It should be, but unclear where I'd put such information... Alvie
  10. Good work Alvie
  11. You're the man, Markus
  12. AFAIK the diodes are just for protection [to make sure we don't kill the VGA monitor], and the caps (which should only be a few pF) are part of a low-pass [although HF] filter. Jack should have more details. You can perfectly live without them, though. Alvie
  13. I have an implementation for it. let me know if I should publish it (I think it's on an non-published ZPUino branch) Alvie
  14. To be more precise, the FPGA boots the initial ZPUino from SPI flash [FPGA design], it starts, waits for 1 second for serial/usb commands and then loads the user code from SPI flash and executes it. Alvie
  15. Not that I know of. It should work flawlessly out of the box. Note that often "writing" is disabled, to save code space. What issues are you encountering ? Only write not working? Alvie