alvieboy

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About alvieboy

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  1. You're the man, Markus
  2. AFAIK the diodes are just for protection [to make sure we don't kill the VGA monitor], and the caps (which should only be a few pF) are part of a low-pass [although HF] filter. Jack should have more details. You can perfectly live without them, though. Alvie
  3. I have an implementation for it. let me know if I should publish it (I think it's on an non-published ZPUino branch) Alvie
  4. To be more precise, the FPGA boots the initial ZPUino from SPI flash [FPGA design], it starts, waits for 1 second for serial/usb commands and then loads the user code from SPI flash and executes it. Alvie
  5. Not that I know of. It should work flawlessly out of the box. Note that often "writing" is disabled, to save code space. What issues are you encountering ? Only write not working? Alvie
  6. No, I never used Microblaze at all. I find the architecture (most notably the function preambles/postambles for C ABI) a bit awkward. And it's commercial Alvie
  7. I believe we also have the generic VGA working on DUO for those resolutions. Alvaro
  8. It should be fixed by now, I think.
  9. We have such an implementation using the SDRAM. If I recall well, it works OK at 640x480x8bit. Ideally you should get a memory which is almost 3 times as fast as the fastest datastream you need (read or write). You will also need to arbiter between the read and write requests, and probably will need a read FIFO to account for the jitter of the arbiter (we do exactly that). You may want to take a look here: https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/devices/video/vga_generic.vhd Alvaro
  10. Indeed. However, we have two FPGA designs. The master designs always loads first, and can set those registers so that when the second (user) design loads, it is already set up. Not sure. I actually think we will not be able to use the method cause PC will always drive DP/DM signals... still to understand and test. I think the idea was to force an USB reset, and that will force DP/DN to go low (Single-Ended zero). May work, may not work... Alvie
  11. Btw, here's the USB wishbone controller: https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/contrib/usb/usbctrl.vhd
  12. Any expertise is welcomed What we have put to work so far (with a PPro and my USB wing) packs a simple USB transceiver, so all PHY-related stuff is actually inside the FPGA. This works well for full-speed (12Mbps) and we have a quite generic USB interface for it, with support for most useful endpoint types, but not all (isochronous is not supported). The internal design we have uses also ULPI, so should be fairly simple (never that simple, is it?) to use USB3300 or other ULPI/UTMI chip. But USB 2.0 puts some emphasis on larger endpoint sizes, and memory is not that big internally. My idea (original idea) was to actually have a EHCI interface to the CPU, but not sure it is worth the effort. Not sure when I will be able to test USB3300, I will let you all know when I do. Alvie
  13. Might well be.. or at least play a role on it. Can you try setting all those actively driven to FAST ?
  14. On the mapping report (.mrp) you should see if your IO pins have dedicated IO registers. +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | CLK | IOB | INPUT | LVTTL | | | | | | | | DRAM_ADDR<0> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | .... | DRAM_CLK | IOB | OUTPUT | LVTTL | | 12 | FAST | ODDR | | | | DRAM_CS_N | IOB | OUTPUT | LVTTL | | 12 | FAST | | | | | DRAM_DQ<0> | IOB | BIDIR | LVTTL | | 12 | FAST | IFF | | | | | | | | | | | OFF | | | | DRAM_DQ<1> | IOB | BIDIR | LVTTL | | 12 | FAST | IFF | | | | | | | | | | | OFF | | | ... | DRAM_DQM<0> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_DQM<1> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_RAS_N | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_WE_N | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | As you can see here, the address lines have OFF in Reg(s) tab, meaning "Output Flip Flop". The Clock line is driven by a ODDR flip flop. The data lines have both OFF and IFF (Input Flip Flop). All other control lines have OFF. This ensures minimal delay from clock to pad, and to chip, and its very important to timing. You seem to have increased one of the timings, though. I wonder it is the same issue we are facing with newer SDRAM parts. Alvie
  15. It may relate to different setup/hold values, and how FPGA routes stuff. Can you check that all your DATA/ADDRESS lines for the SDRAM have IO registers ? Alvie