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About alvieboy

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  1. No, I never used Microblaze at all. I find the architecture (most notably the function preambles/postambles for C ABI) a bit awkward. And it's commercial Alvie
  2. I believe we also have the generic VGA working on DUO for those resolutions. Alvaro
  3. It should be fixed by now, I think.
  4. We have such an implementation using the SDRAM. If I recall well, it works OK at 640x480x8bit. Ideally you should get a memory which is almost 3 times as fast as the fastest datastream you need (read or write). You will also need to arbiter between the read and write requests, and probably will need a read FIFO to account for the jitter of the arbiter (we do exactly that). You may want to take a look here: Alvaro
  5. Indeed. However, we have two FPGA designs. The master designs always loads first, and can set those registers so that when the second (user) design loads, it is already set up. Not sure. I actually think we will not be able to use the method cause PC will always drive DP/DM signals... still to understand and test. I think the idea was to force an USB reset, and that will force DP/DN to go low (Single-Ended zero). May work, may not work... Alvie
  6. Btw, here's the USB wishbone controller:
  7. Any expertise is welcomed What we have put to work so far (with a PPro and my USB wing) packs a simple USB transceiver, so all PHY-related stuff is actually inside the FPGA. This works well for full-speed (12Mbps) and we have a quite generic USB interface for it, with support for most useful endpoint types, but not all (isochronous is not supported). The internal design we have uses also ULPI, so should be fairly simple (never that simple, is it?) to use USB3300 or other ULPI/UTMI chip. But USB 2.0 puts some emphasis on larger endpoint sizes, and memory is not that big internally. My idea (original idea) was to actually have a EHCI interface to the CPU, but not sure it is worth the effort. Not sure when I will be able to test USB3300, I will let you all know when I do. Alvie
  8. Might well be.. or at least play a role on it. Can you try setting all those actively driven to FAST ?
  9. On the mapping report (.mrp) you should see if your IO pins have dedicated IO registers. +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | CLK | IOB | INPUT | LVTTL | | | | | | | | DRAM_ADDR<0> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | .... | DRAM_CLK | IOB | OUTPUT | LVTTL | | 12 | FAST | ODDR | | | | DRAM_CS_N | IOB | OUTPUT | LVTTL | | 12 | FAST | | | | | DRAM_DQ<0> | IOB | BIDIR | LVTTL | | 12 | FAST | IFF | | | | | | | | | | | OFF | | | | DRAM_DQ<1> | IOB | BIDIR | LVTTL | | 12 | FAST | IFF | | | | | | | | | | | OFF | | | ... | DRAM_DQM<0> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_DQM<1> | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_RAS_N | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | | DRAM_WE_N | IOB | OUTPUT | LVTTL | | 12 | FAST | OFF | | | As you can see here, the address lines have OFF in Reg(s) tab, meaning "Output Flip Flop". The Clock line is driven by a ODDR flip flop. The data lines have both OFF and IFF (Input Flip Flop). All other control lines have OFF. This ensures minimal delay from clock to pad, and to chip, and its very important to timing. You seem to have increased one of the timings, though. I wonder it is the same issue we are facing with newer SDRAM parts. Alvie
  10. It may relate to different setup/hold values, and how FPGA routes stuff. Can you check that all your DATA/ADDRESS lines for the SDRAM have IO registers ? Alvie
  11. That's there to support larger devices in the future. Right now we tie that line to '0': DRAM_ADDR(12) <= '0'; Alvie
  12. It's fairly easy to use the SDRAM, once you understand the basics of how our controller works. You can use the controller separately, no need for ZPUino at all. Let me know if I can be of some assistance. We may eventually even come up with a decent how-to Alvie
  13. That's easy. "Design" tab, expand "Synthesize - XST" and choose "View RTL Schematic". Alternatively you can open the .ngr (RTL) or .ngc (Technology) file inside ISE, after synthesis. The RTL view shows you the design prior synthesizing the low-level elements (LUTs, Flip-Flops, so on). The technology shows you how they are mapped into LUTs and FF and so on. This is still prior to mapping, so things can change a bit in the process. Note that due to optimizations sometimes what you see may be a bit "mangled". In that case, enable "Keep Hierarchy" in Synthesis options (right-click on "Synthesize - XST", choose "Process properties"). Glad your problem is fixed now. Alvie
  14. Yes, VHDL is synchronous to the clock, and completely independent of what CPU does. No, all registers (if address is correct) shall at least ACK the transaction (although it may happen that read/writes do not read anything useful or have any side effects). Can you also share the code (.elf) generated ? It may happen that the IO is being directed to a wrong or invalid address.
  15. Tony, can you send me these files that are generated by the ISE build process: .ncd .ngd .syr .mrp (make sure you enable detailed map report, if possible -see options for Map generation) Zip all of them and send to "". I'll try to see what is happening. The only "normal" lockout from the CPU point of view is when it tries to read/write to a IO location and ACK never comes in... Alvie