Jack Gassett

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Everything posted by Jack Gassett

  1. Hello adamada, You should check all of your configuration settings. The easiest way to do that is to open the *.xise file and compare it to an xise file that is successfully generating a bit file that loads to spi flash. You have probably accidentally set the configuration to a quad spi chip or something... Jack.
  2. Hey Brad, The 5V rail is connected directly to the USB connector so you should be able to draw as much as the USB socket can provide. If you are powering from a USB socket then it is limited to 500mA unless you are connecting through a powered hub. The Voltage regulator on the 3.3V rail can supply a maximum of 600mA if I remember correctly. Jack.
  3. Hey Keith, that long 12" cable on the digital side is going to add resistance to the equation too. You might want to take a look at that next. Jack.
  4. Please take a look at the VGA section for the VGA circuit of the Computing Shield: http://papilio.cc/index.php?n=Papilio.ClassicComputingShield#vga This is probably the important part that is affecting your design: The VGA cable should be providing 75 ohm resistance. If you are not using a VGA cable with 75 ohm's then that might be why the colors look dim? Jack.
  5. DesignLab should also have some audio examples that will work with the LogicStart MegaWing audio output. They are ZPUino examples, not straight VHDL examples. Jack.
  6. The Papilio Loader should cause there to be a restart after the bit file is loaded... Maybe there is a bug in the Linux version, try to do a papilio-prog -C command and see if that forces the restart. For the multiple bit files, the spi flash supports that but there is no completed project yet to demonstrate that working... Jack.
  7. Hello, The digital joystick on the LogicStart MegaWing is super easy to use. It is just a digital logic '1' on each directional pin when you move the joystick in that direction. Here is the documentation with the ucf settings: http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing#joystick Or download the LogicStart MegaWing ucf file: Jack.
  8. Hello Thomas, This looks very cool, I've been doing a contract job that is eating up most of my time. But hopefully I can give this a spin this weekend. Thank you for posting it, Dhia is going to get it up on the blog and social media tomorrow. Thanks! Jack.
  9. Hello Thomas, It sounds like you have a good handle on most of the details already. The voltage regulator can provide up to 600mA but a computer will only provide 500mA. If you need the full 600mA then connect through a powered USB hub. The esp8266 will burst up to 300mA when starting but uses much less when running. The piece of the puzzle you are missing is how much the FPGA will use, but unfortunately I cannot give you an easy answer to that. It is highly dependent on the design that you are running on it. There is an excel spreadsheet you can download from Xilinx that will look at your design and tell you what kind of power it will use... It can be super low, when I ran the XPower? spreadsheet on the OLS design when we were running it the estimate was only 10-20mA so we ended up using a 50mA voltage regulator in that design. It never had any power issues which validates that very low power usage for that application... Or it can be pretty high, just depending on your logic... The easiest way to tell for sure is to buy one of these Charger Doctors from ebay. Plug your Papilio into power through it with just your app running and see what the current draw is. Then do the same with esp8266 connected and you should have a very good, real world picture. Jack.
  10. Hello Thomas, Yes, it will continue with SDRAM, we have identified an ISSI SDRAM chip to use instead but there is still some work to be done to verify before we do the next run of boards. I'm also seeing if I can find a supply of the current SDRAM chips to do one more run of the Papilio Pro with the current chip. Jack.
  11. It's not retired but the SDRAM chip that is used is obsolete. We are looking for replacements which will take a little time... Jack.
  12. I don't think its a good idea to connect directly to ground... I think that drive strength is how much current it will provide through that pin under load. So put a load in by connecting a 1k resistor in series with your ammeter and then see what the current is... Jack.
  13. psehorne, We can replace the board for you if you feel confident there is an issue with it. Just send us an email to support@gadgetfactory.net with your shipping address and a link to this email. Jack.
  14. Congratulations on finally breaking this one loose. The scenario like you describe has happened to me several time too. It's so easy to get the blinders on with this type of work. You think you know what the problem is so you just go further and further down the rabbit hole trying to fix it and it turns out to be something simple somewhere else. Good job and I'm sure you will not regret the Oscope. Jack.
  15. You can post your bit file here and one of us can try to load it to our Papilio Pro board and see if it is the same result. That would let us know if it is just your board or the bit file... Jack.
  16. Ah, that is a good idea... the crosstalk can make it kind of work sometimes... That sort of thing has happened to me before. Jack.
  17. No, the scope is absolutely what you need to troubleshoot this. That and a logic analyzer when you need to see what is happening on more then two pins at the same time. I bet you get it figured out in a couple hours with the scope. Jack.
  18. that is an odd one... I would recommend opening up your xise file in a text editor and compare it to a known working xise file... Jack.
  19. Please take a look at the Quickstart guides and see if anything you are doing is different: http://papilio.cc/index.php?n=Papilio.QuickStartGuide http://papilio.cc/index.php?n=Papilio.GettingStartedISE Jack.
  20. Felix, We should put it in the downloads section... I'll ask Dhia to put it up there for us. Jack.
  21. Hello fpga_guy, The output that you pasted looks like a completely normal flash process, I don't see anything to indicate a problem... We should rule out that there is something wrong with the bit file that is preventing it from running from flash (there are configuration settings that can do that...). Can you either use the test bed that Felix so kindly made and linked to or use this Papilio Quickstart bit file to test and see if loading from SPI flash works at all? With the Papilio Pro quickstart you should see every other pin blinking and the ASCII table being output on the serial port at 9600 bps. Jack.
  22. So you are connecting the digital pins r0-r3, g0-g3, b0-b3, and hsync, vsync with jumper wires? Seems like that should work... You should start with troubleshooting the hsync and vsync lines. If those are the only things you connect and they are working correctly then the monitor should say that there is a picture but it will not show anything. But you will get a sync and it will think something is connected. So focus on those first and use a logic analyzer or an oscope to see what you are getting on those lines... Maybe you just have the wrong pin positions or something or maybe the jumpers are disrupting the waveform just enough to change the frequency or something. If you have an oscope just look at the signal and make sure it has the right freq and voltage. Jack.
  23. Hello Luis, When we first developed the board we put them on just in case they were needed but we never ran into any situations where they were. We left them off all VGA variations designed afterwords. I don't even remember the specifics that was so long ago... Jack.
  24. Yes, that is how it works for ZPUino. For a regular bit file the FPGA boots from the SPI flash directly. Jack.
  25. The sketch is loaded into SPI flash. Once you load a sketch and power cycle the sketch is still in effect. Jack.