Jack Gassett

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Everything posted by Jack Gassett

  1. Glad to hear you got this working. Jack
  2. Well, I just tried to see if it works on the Papilio Pro and I didn't get a response using the OLS client. I only have about 15 minutes to put into it this morning unfortunately. Here is the latest version, you can unzip it into the libraries folder of your DesignLab installation and then find the Winsbone_Sump_LA/OLS_CLient example under Examples in DesignLab. You will then need to load the circuit to your board, load the sketch, and open the OLS client and try to connect to it. The status that we left off was that it was 80% working and just needed some bugs in the OLS_CLient sketch to be worked out... Development fell off because we discovered that the performance is not that great. The best that we were seeing was about 30Ms/s... Jack. Wishbone_Sump_LA.zip
  3. So Alvie and I have been talking and we want to work on a Wishbone version of the Sump Blaze Logic Analyzer core. The main benefits of this are: The ability to use SRAM, SDRAM, or DDR ram through the Wishbone bus via DMA transfers. This will get us much more memory available for the Logic Analyzer.It will be much easier to output the captured samples in different formats since it will be C code instead of VHDL code. It will be easy to add support for your favorite Logic Analyzer clients. Not only Jawi's OLS client but special modes for the Saleae client can be easily added as well.So to get the ball rolling on this effort I've made a special version of the Sump Logic Analyzer core that has its control interface mapped to Wishbone bus registers. This version still uses internal BRAM but I've setup a simulation test bench to make the transition to DMA transfers for RAM easier to work out. The branch on github can be found here: https://github.com/GadgetFactory/DesignLab_Examples/tree/Wishbone_Logic_Analyzer The commit is: https://github.com/GadgetFactory/DesignLab_Examples/commit/6019352579070f378304e9f710604b92e0f961cc Or if you prefer a ready to go zip file: Wishbone_Sump_LA.zip Just open the Chip_Designer.xise file, change to simulation mode, and simulate the Simulate_Your_Chip_Design module as the top level. The next step, moving to DMA memory, is something that's beyond my skills. Going to have to defer to Alvie's expertise for the next step, but am hoping to learn from the example of how DMA memory can be used with his new burst controller. Jack.
  4. Sounds great. Jack.
  5. Hello Mr. Minix, I have heard of people reversing the LogicStart MegaWing like in this post: The other option is to go with the Papilio DUO and the LogicStart Shield. The VGA portion of the LogicStart Shield snaps off and gives you access to 16 pins... We are currently out of stock of the DUO right now but will have some 2MBs ready soon, or you can order from Seeed Studio. Jack.
  6. It's weird though, I brought up a fresh OS install using vagrant to pull down an untouched VM image for Ubuntu 16.04 and 16.10 and all I had to do was an "sudo apt-get install default-jre" and run the ubuntu-install.sh file and it worked perfectly. No need to set JAVA_HOME at all. Did you maybe install the JDK instead of the JRE? Maybe that would explain the difference... Jack.
  7. I wonder if maybe it is related to your video card drivers? Here is a discussion about something vaguely related: http://forums.winstep.net/phpBB2/viewtopic.php?f=2&t=8573&p=24560 One of the things they bring up is video card drivers which is not a bad idea to check since it has never happened on any of the systems I've used during development... Jack.
  8. Hello Sleat, That looks annoying, in all the time I have spent developing and working with the IDE I don't recall seeing that happen... Does it go away if you minimize and maximize the app or do an alt-tab to switch between apps quickly? DesignLab was forked from Arduino IDE 1.5.8 so if that was an existing problem with Arduino then it would be brought forward with us. If we can find a commit to the Arduino IDE that solves this problem then we can apply it to DesignLab too. Jack.
  9. I just downloaded and tested Ubuntu 16.04 and 16.10 images. I followed this guide and the only difference was that the install script is called ubuntu-setup.sh now instead of ftdi-user. I also installed the default-jre using apt-get which installed OpenJDK 8 and all went smoothly... Glad you got your working. Jack.
  10. Excellent advice, I got Hamsters OV7670 code working on the Papilio but I did have to rely on the SUMP logic analyzer core to get everything working correctly... It is your best friend with getting something like this working. Otherwise you are flying blind. Jack.
  11. Hello Shahabamo, The problem you are running into is that those variant projects are getting pretty old now. The source code tree has been re-arranged and not all of the variant projects have been updated to reflect the moves. You have two options: Run make in the S6LX9 directory or update the *.prj file in the variant directory to point to the new locations for the source files you are getting errors for. Jack.
  12. Hello Peter, Any luck yet on getting it to run? Java 7 should be the safest version to use... Jack.
  13. Glad you got it worked out Matt. Jack.
  14. The Papilio One can be used as a "Sump" Logic Analyzer just like the Open Bench Logic Sniffer. The Project page is located here. Download the latest binaries here.
  15. Excellent! Glad you are enjoying the journey so far.
  16. Hello Skip, I think the root of the problems you are seeing may be from a misunderstanding about how DesignLab works. I suspect that you are going into the circuit directory and opening the *.xise files directly. That is not going to work, it is important that you open up the Xilinx ISE using the "Load Circuit" icon within DesignLab. DesignLab modifies the xise files and puts all of the correct paths in place when you click the "Load Circuit" icon. If you try to bypass DesignLab and open the xise files directly then you are going to have all types of problems with wrong paths because you are never giving DesignLab the chance to setup the environment... Jack.
  17. Hey Skip, Thank you very much for the pull request, it looks like there are too many auto-generated files that are included though... It makes it hard to determine where the real changes that need to be made reside... I think the best thing at this point is for me to try and re-create what you are seeing. Can you describe the error you get and what you do to get it? Thanks, Jack.
  18. Hello F6EEQ, It might be worth opening up the DVD that you have and double check, there might actually be a linux installer on it... You can also request that Xilinx send you a DVD for free here: https://www.xilinx.com/support/dvd-fulfillment-req-ise.html Jack.
  19. Thanks Skip, if you can send a pull request when you are ready I will merge it in. Do you have the fixes for the path issues too? I thought I had fixed them with the 1.0.8 release but maybe not. Thanks, Jack.
  20. Due to Chinese New Year all production is shut down. When they return in a couple weeks I will look into another batch of boards, it is going to be at least 2 months before another batch can be made... Jack.
  21. Skip, No need to use the OLS client included with DesignLab, it is just for convenience. Not sure what is wrong with RLE, I keep meaning to take a look to see what the problem is but its hard to find time right now... Jack.
  22. Yes indeed, that is the module that I'm using... Jack.
  23. That is actually what I'm doing with Papilio Flex. I'm testing out the method of just using an FTDI 6 pin connector so the board itself is as cheap as humanely possible, but can be expanded out to anything you would need.
  24. If I remember correctly it should be running the Logic_Analyzer.sh script in the DesignLab-1.0.8/tools folder. Can you see if you can manually run that script? Maybe there is an issue with Java on your path? Jack.
  25. With the USB PHY's that we are using if there is no USB core on the FPGA then there is no way to load a bit file to the device without manually pressing the reset button. I'm not happy with that solution and am thinking that it will be best to redo the Papilio Nano with a USB to serial chip instead of the USB PHY. Let the USB PHY be an optional Wing. I also have to work out how the bootloader process is going to work which I will be doing on the Papilio Flex board first. Jack.