Jack Gassett

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Everything posted by Jack Gassett

  1. I've been working on making a build environment that has everything needed to do Papilio development already installed and ready to go, including the Cloud9 IDE. This is a rough start and still needs a lot of work but might be worth checking out. Do the following to get it up and running on your local machine. You need to have Docker installed and working first, then: docker run -v $(pwd):/workspace -p 8181:8181 gassettj/papilio-environment-cloud9 --auth username:password You can get the ip address of the cloud9 instance by doing: docker-machine ls This will give you an ip address under the URL column. You can then open up a web browser at http://<the docker machine ip>:8181 and use username=username and password=password Once you are in cloud9 you will have to upload a Xilinx.lic file to the ~/.Xilinx directory (There is a upload tool built into the file menu). In the Cloud9 IDE you will see a terminal window, in that window type: git clone https://gitlab.com/Papilio-FPGA/papilio-quickstart-vhdl.git cd papilio-quickstart-vhdl/ fusesoc --cores-root=. build webpack_quickstart You should see the project build in the terminal window and you can navigate to the project source files on the left. Once the build is done you can right click on the bit file that is generated, download it, and run it on the papilio pro board. Still needs a lot more work, but is a pretty cool start!
  2. Hey Thomas, I put this together because the number one complaint that people had in the back to basics thread was frustration with downloading and installing the tools and setting up the environment. This solves that problem... Think of it as a lightweight virtual machine, it has all the tools needed pre-installed but without the need to include the OS. Xilinx ISE, fusesoc, zpuino toolchain, a local version of cloud9, and could also include your bonfire toolchain and the arduino toolchain. It has everything pre-installed and configured to build bit files for the papilio board. If I had done this with virtualbox then I would have to include the OS inside virtualbox, we would easily be pushing a 30GB download really quick. With Docker we can setup a VM that does not require the OS and has the benefit of a centralized repository and compresses the download. If I remember correctly you only have to download 4GB or something like that for this setup. If you are already on Linux its super easy to get up and running. Just do a "apt-get install docker.io" and then the docker run command that I posted earlier. Docker does all the rest, it will download the virtual machine (called images in docker) and then run it in a container and bind the port 8181 from the container (think virtual machine) to your local machine port 8181. Then you just fire up a browser, connect to port 8181 and you are in a versio of cloud9 IDE that is running in the container (virtual machine) with a terminal window that has everything setup to make a bit file inside the container. The other thing docker will do is that it will map the workspace inside the container to the directory that you ran the docker run command in so you can work with the source files with cloud9 or any local editor you prefer. You just need to supply a Xilinx.lic file and you are up and running in a couple of minutes... Try it out, its magical. Jack.
  3. Yes, cloud9 has a nice editor with VHDL support. But where it shines is that it integrates the environment needed to run code into a cloud IDE. You just connect to it and start coding, no installs and setup to deal with... Here is what the VHDL editor looks like:
  4. In another discussion about getting back to basics FuseSOC was mentioned as a possible tool to manage HDL libraries. I've been looking over the documentation (which is extremely sparse) and think it might be a good fit. I'm attempting to first setup a simple project to autobuild with it. I added a FuseSOC .core file to this existing project: https://github.com/GadgetFactory/VHDL_Example_Code/tree/master/WebPack_QuickStart Then on a linux machine on AWS I did the following commands: sudo apt-get install python2 python-pip https://github.com/GadgetFactory/fusesoc.git cd fusesoc/ sudo pip install -e . cd .. git clone https://github.com/GadgetFactory/VHDL_Example_Code.git cd VHDL_Example_Code/WebPack_QuickStart/ fusesoc --cores-root=. build quickstart The result is a fully automated build process that creates a WebPack_QuickStart.bit file in the build/quickstart_0/bld-ise/ directory. I was unable to figure out how to make changes to the xise project file for things that we use with the Papilio so I had to fork the project and hard code the necessary changes for now. This is the commit I made: https://github.com/GadgetFactory/fusesoc/commit/5c69ec3a57f23e84d014686d96ea68c3225d1fab I added the following two lines to the tcl script that creates the project: project set "Allow unmatched LOC Constraints" true project set "Create Binary Configuration File" true The first one allows us to use a ucf file that has all the papilio pins defined without throwing up errors. The second line creates a bin file that can be loaded using zpuinoprogrammer. This is a good first step to test out automated builds, up next is using the library management features and then getting it under CI. Jack.
  5. Yes, I hear you, forking is not the long term solution. I forked the project because I needed to add special parameters to the tcl script that creates the .xise project file and I didn't see any support to do so in the code. I also wasn't sure if FuseoSOC was going to be suitable for what I wanted to accomplish so the quickest and easiest thing to do was just hard code what I needed into the part that generates the tcl script. The plan is to circle back around and either code the functionality I need and push it back to the main project or create an issue and request the functionality. Either way, the fork should just be a temporary thing while I'm figuring out the workflows that I need. The papilio base library can be added to a config file from what I've read, so the fork isn't needed for that. I'm not sure I've gotten as far as you have to really see this problem yet. But one thing I was uncertain about was how to update the cache? When I make a change to my base repository I have to wipe out the local cache and do a fuesesoc init again. There must be an easier way that I'm not seeing in the quick help... One of the problems I ran into is that I want to have my ucf files in the papilio-boards.core file and just add it as a dependency. I have to hard code a path that would be changing when the module changes version numbers which is not a great solution. The only thing I can think of so far is to add the ucf files as git submodules... So maybe a hybrid solution of git submodules and fusesoc is the best solution... Yes, absolutely, that is what I was thinking. Part of the problem that people have with using zpuino is that the board files are buried way down in the directory structure. I would like to get all of the files that you need to modify to customize a zpuino instance checked into a top level git project and then use fusesoc to pull in all the supporting files that people don't need to worry about. Would love some help along these lines and also integration with other projects. Also, I would like to branch out to Altera and ICE Papilio boards. I think fusesoc will help with creating and managing a common code base for non xilinx Papilio boards.
  6. So Alvie and I have been talking and we want to work on a Wishbone version of the Sump Blaze Logic Analyzer core. The main benefits of this are: The ability to use SRAM, SDRAM, or DDR ram through the Wishbone bus via DMA transfers. This will get us much more memory available for the Logic Analyzer.It will be much easier to output the captured samples in different formats since it will be C code instead of VHDL code. It will be easy to add support for your favorite Logic Analyzer clients. Not only Jawi's OLS client but special modes for the Saleae client can be easily added as well.So to get the ball rolling on this effort I've made a special version of the Sump Logic Analyzer core that has its control interface mapped to Wishbone bus registers. This version still uses internal BRAM but I've setup a simulation test bench to make the transition to DMA transfers for RAM easier to work out. The branch on github can be found here: https://github.com/GadgetFactory/DesignLab_Examples/tree/Wishbone_Logic_Analyzer The commit is: https://github.com/GadgetFactory/DesignLab_Examples/commit/6019352579070f378304e9f710604b92e0f961cc Or if you prefer a ready to go zip file: Wishbone_Sump_LA.zip Just open the Chip_Designer.xise file, change to simulation mode, and simulate the Simulate_Your_Chip_Design module as the top level. The next step, moving to DMA memory, is something that's beyond my skills. Going to have to defer to Alvie's expertise for the next step, but am hoping to learn from the example of how DMA memory can be used with his new burst controller. Jack.
  7. SUMP Logic analyzer not responding

    What is the behavior when it stops working? More details could help me give you better advice. You might try doubling your sample rate, maybe it not working is just that the sample rate is not high enough? When I test the SUMP core the main things I do is have the serial port send out the ascii table and then make sure that I can capture it. I'm almost 100% certain I did this with the SUMP core in the example you are using... But it's been a while so I don't remember exactly. The example in DesignLab should be the best one to work off, definitely don't use the wishbone interface one, that is not even close to being ready. jtagserver should be easy to port to linux, its a cygwin app under windows if I remember correctly. I just never had the time (and no one showed interest) to make any little changes needed to work under linux. Jack
  8. Wishbone version of the Sump Blaze Logic Analyzer

    Hey Blake, Are you talking about Jawi's OLS client or the original sump client? I don't recall ever seeing the problem you are talking about...
  9. Ok, I made more progress today and have got ZPUino fusesoc cores designed and a vanilla version of ZPUino synthesizing for the Papilio Pro. These are the steps to recreate what I've done: git clone https://github.com/GadgetFactory/fusesoc.git cd fusesoc pip2 install -e . fusesoc init cd ~ git clone https://gitlab.com/Papilio-FPGA/Papilio-ZPUino-SOC.git cd Papilio-ZPUino-SOC fusesoc --cores-root=. build papilio-pro-zpuinoSOC The bin an bit files can then be found under: build/papilio-pro-zpuinoSOC_0/bld-ise/ It's also possible to make the ZPUino SOC the old fashioned way by doing: git clone https://gitlab.com/Papilio-FPGA/Papilio-ZPUino-SOC.git git submodule update --init --recursive make Next steps are to make a core to generate the bootloader.vhd file and to get this working in an automated fashion in Docker.
  10. Best place to order from the EU

    I'll see if we can start putting the invoice on the outside... We should be getting more Pro's in a couple of weeks if all goes well. Jack.
  11. Download Error YAVGA

    Ah! Sweet, thank you. I'm attaching it here too in case wayback machine loses it. Jack. YAVGA_Source_1.0.zip
  12. Modifying the libraries

    Actually there is a readme that explains better how to setup the libraries so you can modify them. I'd make a fork of the github repository and then follow the readme, then you can track your changes back to github. https://github.com/GadgetFactory/DesignLab_Examples
  13. Modifying the libraries

    Hello keesj, Generally what I would do if I was going to make changes to the libraries was to delete the library from the DesignLab-1.0.8/libraries folder and put it in my home directory under the Designlab folder. I don't remember the exact path but you should be a directory there for sketches and if there is a subdirectory for libraries it will use that. I would copy this entire github repository there and make my changes there and post them back up to github. https://github.com/GadgetFactory/DesignLab_Examples Also, please be advised that I am working towards a more sane method of managing libraries and code examples. It's just getting started but I think using FuseSoc is going to help us make things clearer, easier, and not depend on the Arduino IDE. The conversation is starting up here:
  14. CaseSensitive bit

    Hello keesj, Thank you for the heads up, I will see if I can put a change into github for this problem. Jack.
  15. Registration to the forum

    Ok, thanks for the heads up, we will look into what is going on... Jack
  16. Best place to order from the EU

    Here is the list of distributors, not sure they are all in stock at the moment though. http://store.gadgetfactory.net/distributors Jack.
  17. I came across this article recently and wondered if anyone has any more details about this? https://www.patreon.com/posts/12886887 Jack.
  18. Wishbone version of the Sump Blaze Logic Analyzer

    Hello Blake, I'm pretty sure you can use Eclipse IDE to debug Jawi's OLS client. Jawi has some instructions for how to use Eclipse on his github page: https://github.com/jawi/ols Thats what I was using and I remember it was pretty helpful. You can also use a serial port application that is capable of sending binary data such as hercules or realterm. Here are my notes from debugging with the serial port: Usefull posting that shows a breakdown of what command to send for debugging in hercules: http://dangerousprototypes.com/forum/index.php?topic=549.0 To reset 00 00 00 00 00 02 To Init C0 00 00 00 00 C1 00 00 00 00 C2 00 00 00 08 80 00 00 00 00 81 ff 01 ff 01 82 02 00 00 00 To start capture 01 The time for 9 cycles as measured above should be (1/115200)*9 = 78us Bad good character 78 80 0b00110001 78 80 0b01000001 76 80 0b01001100 78 75 0b01010011 Jack.
  19. Help with Hamster Book tutorial (newbie stupid question inside)

    Hello, I haven’t tried it myself but maybe you could use excel or mathcad or maybe even wolframalpha. Sent from my iPhone using Tapatalk
  20. Hello, There is a dual channel USB chip on the Papilio board. The first channel is used to program the FPGA over JTAG and the second channel is used for UART communications. You should see the ASCII table output on the second channel... Here are some guides to show how it works: http://papilio.cc/index.php?n=Papilio.GettingStarted - Go to the very end to see how to use Putty to see the ASCII table. http://gadgetfactory.net/learn/2015/04/03/designlab-using-the-ide-for-the-first-time/ http://gadgetfactory.net/learn/2015/04/03/designlab-hello-world/ Designlab has built in USB communications. The screenprint that you included above looks like it loaded the quickstart bit file just fine. Its is unusual to see that last bit, but it looks like it is working overall. Please be sure to power the device using the USB port and not the external power supply. There shouldn't be any need to power from the external power supply because all of the examples work fine with the power supplied by the USB port. The external power supply was included just in case there was ever a project that needed more then 500mA of power. There has never been a Papilio project that has needed that much power so it is highly recommended to not use the external power connector. If you do use it, you want to avoid using a voltage much higher then 6.5V. Higher then that causes the voltage regulators to generate too much heat. Jack.
  21. Hello Henrik, Sorry you are having problems, lets work through them and see if we can figure out if anything is broken. If anything is not working as it should we will make sure that you get a working board, whether from Seeed or us directly. For the Papilio Pro board itself, this is a good place to get started: http://papilio.cc/index.php?n=Papilio.QuickStartGuide There is a quick start bit file that can be downloaded here: http://papilio.cc/sketches/Quickstart-Papilio_Pro_LX9-v1.5.bit You should see every other pin toggle and you should see an ASCII table output on the serial port. For the very latest code for the RetroCade and Arcade MegaWings please download the DesignLab IDE here: There is an example project for the RetroCade that includes the latest bit file and the latest source code for the RetroCade. There is also an example project for the Arcade Megawing that will output video and music so that you can verify that the hardware works. You will find both projects when you open DesignLab and see the initial table of contents page, just use find to get to them. The source code for the Papilio Pro Quickstart can also be found here... Hope this helps and keep us posted. Jack.
  22. Wishbone version of the Sump Blaze Logic Analyzer

    There are some changes that need to be made to the configuration file for the Sump logic analyzer client to accept larger sizes from what I remember... Also, around 30Mhz was the fastest speed I remember this working at and there were some problems at the start and end of the capture that I didn't get working. If you send a series of ASCII characters over the serial port and capture them you will see the problem. Jack
  23. Computer Space

    Wow, I don't think I ever saw a computer space game when I was a kid... I'd love to get something like this going with an automatic build, but not sure how to deal with the ROM file... Actually I'd like to get all of the arcade games sythesizing with CI... Jack.
  24. Wishbone version of the Sump Blaze Logic Analyzer

    Great, are you able to get it to work? Keep us posted... Jack.
  25. Wishbone version of the Sump Blaze Logic Analyzer

    Hey Blake, you shouldn’t change the wb core to the top level. Leave the file that is the top level when you open the project as the top level. Then select that and hit generate programming file. Sent from my iPhone using Tapatalk