Jack Gassett

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Everything posted by Jack Gassett

  1. Hello Thomas, Yes, it will continue with SDRAM, we have identified an ISSI SDRAM chip to use instead but there is still some work to be done to verify before we do the next run of boards. I'm also seeing if I can find a supply of the current SDRAM chips to do one more run of the Papilio Pro with the current chip. Jack.
  2. It's not retired but the SDRAM chip that is used is obsolete. We are looking for replacements which will take a little time... Jack.
  3. I don't think its a good idea to connect directly to ground... I think that drive strength is how much current it will provide through that pin under load. So put a load in by connecting a 1k resistor in series with your ammeter and then see what the current is... Jack.
  4. psehorne, We can replace the board for you if you feel confident there is an issue with it. Just send us an email to support@gadgetfactory.net with your shipping address and a link to this email. Jack.
  5. Congratulations on finally breaking this one loose. The scenario like you describe has happened to me several time too. It's so easy to get the blinders on with this type of work. You think you know what the problem is so you just go further and further down the rabbit hole trying to fix it and it turns out to be something simple somewhere else. Good job and I'm sure you will not regret the Oscope. Jack.
  6. You can post your bit file here and one of us can try to load it to our Papilio Pro board and see if it is the same result. That would let us know if it is just your board or the bit file... Jack.
  7. Ah, that is a good idea... the crosstalk can make it kind of work sometimes... That sort of thing has happened to me before. Jack.
  8. No, the scope is absolutely what you need to troubleshoot this. That and a logic analyzer when you need to see what is happening on more then two pins at the same time. I bet you get it figured out in a couple hours with the scope. Jack.
  9. that is an odd one... I would recommend opening up your xise file in a text editor and compare it to a known working xise file... Jack.
  10. Please take a look at the Quickstart guides and see if anything you are doing is different: http://papilio.cc/index.php?n=Papilio.QuickStartGuide http://papilio.cc/index.php?n=Papilio.GettingStartedISE Jack.
  11. Felix, We should put it in the downloads section... I'll ask Dhia to put it up there for us. Jack.
  12. Hello fpga_guy, The output that you pasted looks like a completely normal flash process, I don't see anything to indicate a problem... We should rule out that there is something wrong with the bit file that is preventing it from running from flash (there are configuration settings that can do that...). Can you either use the test bed that Felix so kindly made and linked to or use this Papilio Quickstart bit file to test and see if loading from SPI flash works at all? With the Papilio Pro quickstart you should see every other pin blinking and the ASCII table being output on the serial port at 9600 bps. Jack.
  13. So you are connecting the digital pins r0-r3, g0-g3, b0-b3, and hsync, vsync with jumper wires? Seems like that should work... You should start with troubleshooting the hsync and vsync lines. If those are the only things you connect and they are working correctly then the monitor should say that there is a picture but it will not show anything. But you will get a sync and it will think something is connected. So focus on those first and use a logic analyzer or an oscope to see what you are getting on those lines... Maybe you just have the wrong pin positions or something or maybe the jumpers are disrupting the waveform just enough to change the frequency or something. If you have an oscope just look at the signal and make sure it has the right freq and voltage. Jack.
  14. Hello Luis, When we first developed the board we put them on just in case they were needed but we never ran into any situations where they were. We left them off all VGA variations designed afterwords. I don't even remember the specifics that was so long ago... Jack.
  15. Yes, that is how it works for ZPUino. For a regular bit file the FPGA boots from the SPI flash directly. Jack.
  16. The sketch is loaded into SPI flash. Once you load a sketch and power cycle the sketch is still in effect. Jack.
  17. Burn bootloader is no longer used in DesignLab. Use the "Load Circuit" icon instead.
  18. Hey there gimme_tech! Welcome to the forum, please don't hesitate to ask questions and we will help as much as we can. Jack
  19. Hello, Working out the manufacturing, funding, and bringing it to market has been a challenge so far. Right now I have some eCogs and the Arduino Pro Mini version available at the Gadget Factory store. I also have enough boards to sell the NodeMCU version as well but do not have it in the store yet due to the documentation not being done yet. If you have a project in mind and would like a board just let me know. Jack.
  20. Hey everyone, I'm working on a new product line for GadgetFactory that might you might find interesting. It's called GadgetBox and in a nutshell it is an Arduino that solves the shield stacking problem and fits into a nice sleek case. There are eCogs - which are like Wings - that form the top of the case when they are plugged into the board. Don't get me wrong, I love FPGAs but sometimes they are just too expensive for simple things. GadgtBox is meant to take a proven and affordable platform, the Arduino Leonardo, and do some innovations that will hopefully solve the problems people have with it. The biggest problem I see is shield stacking and the ugly mess of wires/pcbs that you end up with when you make something with it! GadgetBox is going to be super inexpensive - hopefully less then $20 and result in an IoT device you won't hesitate to deploy in your house. To learn more check out the daily progress over at Hackaday.io. Jack.
  21. Glad to hear you got this working. Jack
  22. Well, I just tried to see if it works on the Papilio Pro and I didn't get a response using the OLS client. I only have about 15 minutes to put into it this morning unfortunately. Here is the latest version, you can unzip it into the libraries folder of your DesignLab installation and then find the Winsbone_Sump_LA/OLS_CLient example under Examples in DesignLab. You will then need to load the circuit to your board, load the sketch, and open the OLS client and try to connect to it. The status that we left off was that it was 80% working and just needed some bugs in the OLS_CLient sketch to be worked out... Development fell off because we discovered that the performance is not that great. The best that we were seeing was about 30Ms/s... Jack. Wishbone_Sump_LA.zip
  23. So Alvie and I have been talking and we want to work on a Wishbone version of the Sump Blaze Logic Analyzer core. The main benefits of this are: The ability to use SRAM, SDRAM, or DDR ram through the Wishbone bus via DMA transfers. This will get us much more memory available for the Logic Analyzer.It will be much easier to output the captured samples in different formats since it will be C code instead of VHDL code. It will be easy to add support for your favorite Logic Analyzer clients. Not only Jawi's OLS client but special modes for the Saleae client can be easily added as well.So to get the ball rolling on this effort I've made a special version of the Sump Logic Analyzer core that has its control interface mapped to Wishbone bus registers. This version still uses internal BRAM but I've setup a simulation test bench to make the transition to DMA transfers for RAM easier to work out. The branch on github can be found here: https://github.com/GadgetFactory/DesignLab_Examples/tree/Wishbone_Logic_Analyzer The commit is: https://github.com/GadgetFactory/DesignLab_Examples/commit/6019352579070f378304e9f710604b92e0f961cc Or if you prefer a ready to go zip file: Wishbone_Sump_LA.zip Just open the Chip_Designer.xise file, change to simulation mode, and simulate the Simulate_Your_Chip_Design module as the top level. The next step, moving to DMA memory, is something that's beyond my skills. Going to have to defer to Alvie's expertise for the next step, but am hoping to learn from the example of how DMA memory can be used with his new burst controller. Jack.
  24. Sounds great. Jack.
  25. Hello Mr. Minix, I have heard of people reversing the LogicStart MegaWing like in this post: The other option is to go with the Papilio DUO and the LogicStart Shield. The VGA portion of the LogicStart Shield snaps off and gives you access to 16 pins... We are currently out of stock of the DUO right now but will have some 2MBs ready soon, or you can order from Seeed Studio. Jack.