Jack Gassett

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Everything posted by Jack Gassett

  1. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable.
  2. The VGALiquidCrystal library converts sketches that will run on an HD44780 LCD display to sketches that will run on a VGA monitor. This library is derived from the Arduino LiquidCrystal library and aims to provide maximum compatibility. VGALiquidCrystal Wiki Page. Get started with the ZPUino "LogicStart" bit file.
  3. Want to overlay a virtual 7 Segment display over your VGA projects? Look no further, this code will work with LogicStart MegaWing, Arcade MegaWing, or VGA Wings. Virtual 7 Segment Wiki Page Virtual 7 Segment Source Code on Google Code
  4. Kevin Lindsey aka "Thelonious" has been writing VHDL code for the Papilio almost since the beginning of the Papilio. His github page has a nice collection of example projects that should work with the LogicStart MegaWing. Main Github page. VGA Generator 7-Segment driver Sound Out
  5. This bit file loads the ZPUino soft processor with 160x120x8 VGA Output to the Papilio One 500K board and connects the VGA output to the LogicStart MegaWing. This ZPUino variant is derived from the "Hyperion" (Lord of Light) variant. Download the bit file. VGA library reference is here. Source code for the LogicStart variant. Get Started with the ZPUino.
  6. Version 1.0

    351 downloads

    This bit file loads the ZPUino soft processor with 160x120x8 VGA Output to the Papilio One 500K board and connects the VGA output to the LogicStart MegaWing. This ZPUino variant is derived from the "Hyperion" (God of Light) variant. VGA library reference is here. Source code for the LogicStart variant. Get Started with the ZPUino.
  7. Mike Field wrote a great ebook to help beginners learn VHDL and FPGA technology. We asked Mike what would be the perfect hardware for his proposed book and the end result was the LogicStart MegaWing! Download pdf version of Intro To Spartan FPGA. Find all code examples on the ebook's github repository. Wiki page with more material that pre-dates the book.
  8. Version 1.2c

    3,886 downloads

    Generic UCF for the LogicStart MegaWing targeting the Papilio One
  9. Ahhh, its so nice to have people finding these types of problems. I'll look at the HDL and see if I can locate the problem. Jack.
  10. For the Arcade Blaster source code, visit the github repository. To report any bugs, issues, or feature requests; visit the github issues page.
  11. For the very latest source code visit the github repository.
  12. Version 2.8

    25,082 downloads

    Load bitstreams generated by Xilinx ISE to the Papilio One with a Java GUI or scripts. If you need more informations about the Papilio Loader including requirements, installation and much more check the Papilio Uploader wiki page here. Version 2.7+ includes signed drivers for Windows 8. There are now installers for Windows, Linux, and Mac OS X.
  13. Version 1.1b

    1,476 downloads

    Generic UCF for Arcade MegaWing targeting the Papilio Pro and Papilio One.
  14. Version 1.5

    1,572 downloads

    The Pin Converter tool is used to generate all Papilio UCF files. Use it to make your own UCF files! When creating an HDL design, eventually you may want to relocate your wing pin assignment. For instance, you may be moving your design to another type of board or to another location on the same board. The pin_converter project provides a tool to help with this. Created by Thelonious and maintained on GitHub: https://github.com/t...s/pin_converter
  15. Version 1.1

    5,481 downloads

    The Papilio Pro board implements SDRAM instead of SRAM. It also has switching voltage regulators which means no heat will be generated on the board. This board is still in prototype stage.
  16. Version 1.0

    403 downloads

    The Papilio Plus is a Papilo board with SRAM that is still in the prototyping phase. This is the generic ucf file for that board.
  17. Version 1.1

    4,067 downloads

    Generic UCF file for the Papilio One FPGA board.
  18. I'm sorry, so many things have been coming at me at once that I haven't had a chance to try this out. But believe me, it is on my list of things to do! As soon as things calm down a bit I will give this a spin. Jack.
  19. Watch a video with the setup in action – (Original Tweet) Close up picture of custom PCB – (Original Tweet) Quicklinks: Original project page VHDL code on Github
  20. Sounds like a fun project, we look forward to following it. Have you seen the AVR8 and ZPUino soft processors? They are Arduino compatible soft processors that let you run sketches without the arduino hardware. Jack.
  21. Victor, Hmmm, ok, I didn't do much testing beyond with capturing a signal on the build. I suspect what you are seeing could be related to the external trigger, we should look into how that is setup. With the OLS the trigger lines are much more isolated, with the Papilio the headers are right next to each other and can easily "bleed" over. We should put a pullup or pulldown resistor clause on the external trigger line in the ucf or disable it completely if it is the problem. Jakc.
  22. Victor, I just synth'ed the design for the Papilio One 500K and tested it with the Papilio One 500K board at 115200bps. Seems to work fine with Jawi's OLS client. I checked the bit file into github, it can be downloaded here. Hopefully that works for you and provides a frame of reference to get your own synthesis working. Jack.
  23. Victor, Are you using the Sump classic or Jawi's OLS client? Sump classic has a timeout that is too short and does not always work, give it a try with Jawi's OLS client. Jack.
  24. Victor, I did the updates to the core in order to get it working with the new Spartan 6 boards that have 4Mb or SRAM available. Everything works good, but I haven't done any testing at higher speeds yet. Since my focus was more on testing with the new boards I did not generate any files for the 500K boards. I think the default bit rate is 115200, there is a setting in the top level vhd file that you can modify to change the speed. I'll PM you with the FT232H design, I'm just not ready to release it in the wild yet. Jack.
  25. Hello Victor, I did check the much nicer and cleaner version of the VHDL Sump "Blaze" core into github. The latest tag that can be directly downloaded is here. I've played around with increasing the speed with the "Blaze" core and have got it up to just under 1Mb/s but I can't get it to work reliably above that. I'm thinking that the Xilinx UART core may need to be integrated to get speeds up to 3Mb/s. There are comments in the top level file about how to adjust the speed, a lot of the work I did was with making the uart core more reliable and easier to understand. Well, we still hope to bring that design to market, until that happens it doesn't make sense to release the source files. Once we have the product being manufactured we will release the files. For now we have made the compromise of making the PCB available from BatchPCB for the people who want to try it out. Thank you for the update on the BOM, I'll look at getting that updated. Thanks! Jack.