Jack Gassett

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About Jack Gassett

  • Rank
    Aspiring Inventor
  • Birthday 03/12/1974

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  • Website URL http://www.gadgetfactory.net

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  • Gender Male
  • Location Westminster Colorado
  • Interests Snowboarding, electronics, Open Source Hardware, guitar.
  1. Sounds cool, can you post any pictures or video of it in action?
  2. A lot of good advice and ideas. I like Multicomp too, maybe it is a perfect candidate to put up on the new GitLab space and get it doing CI for all the Papilio boards. I've been thinking a lot about the libraries idea, it just needs some common way to connect all the pieces together. Maybe wishbone could do the trick, if we make a wishbone connector without a processor that can just send sequential commands to the wishbone bus to set components up and basic tasks... I envision something like how Alvie has ZPUino setup with wishbone slots so you just connect each wishbone component to a slot and then something simple to control it all. Something like the wishbone testbench that Alvie setup too... But I think the key thing is that I want to work on stuff that people can use... Jack.
  3. Hello everyone, its been quiet in the forums and at GadgetFactory in general. Just wanted to do a quick update and talk about future direction. First of all, I had a bit of a change up in the last six months. With two new boys in the last couple of years I had to make the decision to move on from working full time on Papilio boards and get a full time job. I've been quiet because it has taken a little time to adjust to working at the new job and continuing work on Papilio boards. I think I finally have things figured out and have a good schedule to work on both. Since time is limited I want to focus on getting back to basics with the Papilio FPGA boards. I think that the DesignLab efforts have not really been useful for many people and it is too much to keep maintaining it going forward. The approach of using the schematic editor has just not worked out as well as I hoped it would and overall it is too hard for anyone to contribute to DesignLab. Lesson learned, I need to get back to accepted industry standard techniques and back to VHDL/Verilog going forward. I'd like to start migrating all of the stuff that is currently in DesignLab into smaller and easier to maintain projects. To those ends this is how I'm thinking to proceed: What is needed (what DesignLab currently does that we want to keep): A way to manage libraries - people need an easier way to add VHDL/Verilog libraries to their projects then what Xilinx ISE provides. A repository for ZPUino Soft Processor projects - DesignLab has several ZPUino SOC projects embedded within it. We need to provide these projects outside of DesignLab. Arduino Integration - We need to make all the sketches from DesignLab available in the latest version of Arduino IDE or a cloud IDE. (Nice to have) Continuous Integration for the automatic generation of bit files for the ZPUino projects. (Nice to have) Xilinx ISE build environment in the cloud. (Nice to have) Cloud based IDE instead of Arduino IDE. Ideas to get there: I like the way node.js manages libraries. I'm thinking to use npm for the libraries and then write node.js code to add libraries to the .xise and .prj files when they are added with npm. Github is the first place that comes to mind but the problem is that it is too hard to organize projects there. I have so many projects there that it is hard for anyone to find anything and there is no good way to organize projects. GitLab allows directories and subdirectories and they have Continuous Integration functionality built in. Perfect for number 4 above. The Arduino IDE has come a long way since we forked from it for DesignLab. THey have made it much easier to add custom boards and programmers. There really should be no need for a fork anymore, we just need to make a custom programmer, board type, and libraries. As mention in 2, GitLab has continuous integration built in. I've already tested it out and have it up and running for a couple ZPUino projects. I have my own personal Xilinx ISE and ZPUino build environment setup as an AMI at Amazon AWS. When I do any development work I just spin up the AMI as a spot instance at Amazon. When I commit code to GitLab it connects to the runner in the running instance at Amazon and kicks off the build process there. It then published the bin and bit files as artifacts that I can then download and run on my board. I can even see all the build logs... If we could publish an AMI or Docker image that has the entire build environment ready to go and people just download and add a Xilinx license file then this might greatly help alleviate the pain of downloading and setting up the tools. What is described in step 5 above is a little tedious when it comes to actually development. It would be nice to use a cloud development IDE like cloud9 for development and have the building happen on a docker instance or something... Jack.
  4. Ha, sorry James, I haven't had a chance to try it out. What controller are you using with it? A trackball? Jack.
  5. I would start out with tutorials at the learn website: http://learn.gadgetfactory.net/ Download DesignLab and try out the Papilio Pro examples there. Then check out the free eBook:
  6. I just bought Papilio Pro with the LogicStart Shield.

    Installed Driver to Windows 10 OK. Board recognized as COM 7 and COM 8 for the Papilio Pro Board.

    Papilio Loader for Windows is also installed OK.

    Papilio Pro LX9 QuickStart bit file is also verified board is recognized

    So next are DesignLab IDE and Web Pack ISE Installations ?

    Please help me to start for both Papilio Pro and LogicStart Shield since I am very new with the FPGA and your boards and I am very interested of learning to put them to work. How can I verify both are working, please ?



  7. Hello, it is forked from the Arduino 1.5.8 code. There should not be any conflict with installing both Arduino and DesignLab IDE, I personally have both installed. There have been lots of changes to the Arduino IDE since 1.5.8 that are not in DesignLab... I've actually been thinking to just make a board definition and library that can be used with the latest version of Arduino IDE... Jack.
  8. Hello Brandon, Glad you got it working and thank you for the pull request. I'm actually thinking through a reboot of the source code at the moment. Getting away from DesignLab, the schematic based approach just didn't garner much interest, and going to a node.js solution with examples synthesized with a CI backend on Gitlab. I've actually started a couple of projects with CI at Gitlab and am still working through how to manage VHDL/Verilog libraries with node.js before I proceed. Hopefully I can do a reboot and get everything easier to find and maintain... Jack.
  9. Hello Thomas, I'm sorry you have not received your order yet. I will ask Dhia to follow up with you again to see if we can get to the bottom of this. Jack.
  10. Hello Matt, I think I'm not totally following along what the problem is, but let me try. I see in the picture above that you are connecting wb_rst_i which is a single port to c[31:0] which is a mismatch of a bus with a single element. I'm not sure if that is what you are talking about but if you need to connect wb_rst_i to one of the elements of c[31:0] then you can use a bus tap to expose just one of the signals. This shows how to accomplish that: http://gadgetfactory.net/learn/2015/03/30/designlab-basics/ Jack.
  11. Hello Brandon, Those examples use a SPI controller connected to the wishbone bus of the ZPUino. So the location of the SCK, MOSI, and MISO pins are determined by how you connect the SPI controller in your FPGA circuit. Take a look at the examples in DesignLab and look at the FPGA circuit portion to see how they are connected. The error you are getting is most likely caused by not loading a zpuino circuit to your FPGA that has the SPI master... It is also possible to connect the SCK, MOSI, and MISO pins to the flex pins in a Designlab circuit, this lets you move those pins to any physical pin of the FPGA with your code. There should be examples of how to do this in DesignLab too. Jack
  12. There is examples of controlling the RGB LED matrix panels in DesignLab, it could probably be made to work with the newer rgb led's... Jack.
  13. Yes, it will have the jtag header which will be totally open for an external jtag programmer. Sent from my iPhone using Tapatalk
  14. I might look into doing another batch of Papilio One 250ks soon. But overall, I'm working on a new Papilio design that will replace the Papilio One and Papilio Pro boards with a single board called the Papilio Unity. This board will use much lower priced components and should get the price for a Spartan 6 based design hopefully down to the 250k pricing. It uses lower cost voltage regulators, the cp2104 USB to serial chip, and provides a socket for a memory upgrade. The trick with this board is that we don't need the expensive FTDI JTAG capable chip because we are making a boot loader, like the arduino has. Programming the SPI flash is much faster with this new board. It takes 20 seconds or so on existing boards and is 5 seconds on the new board. The design is working well and we are just getting everything in order before making the first batch. Sent from my iPhone using Tapatalk
  15. Yay, glad you got it working. If you want to trade it out for a new one just send us an email at support@gadgetfactory.net and include a link to this forum thread. Thanks, Jack.