Jack Gassett

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About Jack Gassett

  • Rank
    Aspiring Inventor
  • Birthday 03/12/1974

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  • Website URL http://www.gadgetfactory.net

Profile Information

  • Gender Male
  • Location Westminster Colorado
  • Interests Snowboarding, electronics, Open Source Hardware, guitar.
  1. Yay, glad you got it working. If you want to trade it out for a new one just send us an email at support@gadgetfactory.net and include a link to this forum thread. Thanks, Jack.
  2. You need to use make to synthesize the project.
  3. Hello, It's black boxed because it greatly speeds up the synthesis time for the end user and most people have no need to modify ZPUino, just the peripherals attached to it. The source code for the black box is here: https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/boards/papilio_one/s3e250/variants/designlab Jack.
  4. Sorry, that site has been offline for quite some time now. Jack.
  5. Sweet! I'm going to put this on my list of things to get setup in the office. Jack.
  6. You should be able to just select watchdog.v in Xilinx ISE and then go under processes. There should be an option to generate a symbol which should generate the symbol for you. Jack.
  7. That should be related to what board you have selected. That message usually means that there is not an example for the board that you have selected. If you hit CTRL-K in DesignLab and look in the circuits directory you should see what boards are supported by the example. I also usually put in the notes at the top of the sketch what boards are supported. Jack
  8. Hmmm, this is interesting. Was this with the Wii-Chucks that we are selling from the Gadget Factory store? I'm pretty sure I tested with those but maybe I got something different the last time I ordered... Jack.
  9. Or try this bit file: 1.3.1 should be latest version with LCD fix. Jack.
  10. Hello Anthony, What version of the RetroCade code are you running? I think if you try the very latest version by downloading the DesignLab software and using that to upload the latest code you might see the problems go away. Jack.
  11. Hello Blake, Sorry for the slow response, I've been on a job which was running late every night last week and then Fathers day weekend this weekend... I should get some time this wednesday to take a look at this and help out. Jack.
  12. Hello Blake, Unfortunately I won't get much time to put together an example until next weekend so I will try to talk you through what you need to do. If you look at the image below (from the tutorial) you will see that the Wishbone_to_Registers_x10 symbol exposes the pads for 10 different registers. So anything you connect to them will be readable from your C code on the AVR. In the example below the input is connected to the output, this just means that the registers echo whatever to put in from the C code on the AVR. For your application you will want to remove those wires connecting the inputs to the outputs. Then experiment with connecting VCC and then GND to the register0_in and then verifying that you read back a zero or one from your C code. You can also wire the register0_out to an I/O marker (connected to a physical pin on the Papilio Board) and then verify that you can write to register0 in your code and see the physical pin has the corresponding change. You could then find the example that shows how to make a counter in the schematic editor and implement it and then connect the counters output into the register0_in. One important thing that I just noticed is that each register is 32 bits so it is not as simple as just connecting register0_in to an I/O marker or VCC or GND. You will need to connect those single signals to register0_in(0) or register0_out(0) and read the first bit of the 32 bit wide register. You will want to use a bus tap to accomplish that. There is a tutorial here. Once you get comfortable with doing this from the schematic editor then move on to VHDL. You will want to make a VHDL module that outputs your counter as a port at its top level. Start with making a module that just outputs a 0 or 1 from a port at the top level. After you have created the VHDL module (as a file included in your project) then right click on that file in your file hierarchy list on the left side of ISE and there should be an option to turn the VHDL file into a symbol. Once you successfully run the command to generate a symbol from your VHDL file you should then be able to find it in the symbol navigator and add it to your schematic. Then you connect it to the pads of the Wishbone_to_Registers_x10 symbol. Hope this gets you rolling in the right direction. Jack.
  13. In the meantime, try to comment out this section like it says: //Comment out this section for Papilio One. #ifdef __ZPUINO_PAPILIO_PRO__ #include <SD.h> #include "SmallFS.h" #include "modplayer.h" #include "ramFS.h" #include "cbuffer.h" MODPLAYER modplayer; #endif Like this: //Comment out this section for Papilio One. //#ifdef __ZPUINO_PAPILIO_PRO__ // #include <SD.h> // #include "SmallFS.h" // #include "modplayer.h" // #include "ramFS.h" // #include "cbuffer.h" // MODPLAYER modplayer; //#endif
  14. OK, I will try to take a look at this tonight and get back to you. Jack.
  15. I have never tried out the ethernet shield with the Papilio DUO so not sure what the problem is that you are running into... If you load a blank circuit to the FPGA side then there should not be any conflicts... You could also try to use one of these types of ethernet modules: http://store.gadgetfactory.net/ethernet-module/ Jack.