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  1. Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
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  2. Hello, I've just returned from DConf 2017, in Berlin. There I gave a talk on how to use an extension of the D programming language (DHDL) to design hardware. I showed a demo of Classic Empire, a game written by Walter Bright (the original creator of D), running on a Papilio Pro, inside a soft-core RISC-V CPU, plus my own handmade "wing" IO accessories and respective controller IP blocks (VGA, 7-segment, sound, etc.). You can see a quick demo below: You can also see the full talk, if it sparks your interest: Thanks to the generosity of GadgetFactory, we raffled a Papilio Pro and some accessories to the participants of the talk: Gauging from his reaction, Vang Le was very surprised and happy to be the winner, and he's looking forward to exploring the world of FPGAs. In my demo I loaded the binary code for the game through the USB/UART, using a custom utility. In the next few months I plan to further tweak this demo, so that the game code is loaded from flash and it works with standard GadgetFactory wings. When that is done, I'll provide the bit stream files for the combined hardware design + the game. Walter Bright has indicated that he would provide permission for the FPGA version of the game to be distributed freely, so GadgetFactory could use it for its showcase. Later, I will provide the source code for my whole setup; I used the LDC 2 D compiler with the (old) LLVM RISC-V backend, and I had to workaround a lot of bugs of invalid RISC-V code. When the new LLVM RISC-V backend is released I expect all of that to be alleviated or completely fixed, which will help with the release of the complete demo setup. I'll keep providing updates and feedback here on the GadgetFactory forums. You can also follow me on Twitter (@Luis3m), or email me if you have any questions (http://www.luismarques.eu/about). Also, a shout-out goes to Mike Field, whose book / tutorial helped me get started with FPGAs and hardware design. I shared the love for his book with some conference participants :-) So long, Luís
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  3. Hi all, over the last half year I have implemented a processor and surrounding SoC bringing the RISC-V ISA (http://riscv.org) to the Papilio Pro. It implements the 32Bit integer subset (RV32IM). The project is hosted on Gitub (https://github.com/bonfireprocessor). It still needs some additional documentation, cleanup and ready-to-run ISE projects to make it easy reproducable for others. But I post this link now, to find out if anybody is interested in my work. I will soon also post a bitstream here so anybody with access to a Papilio Pro can play with it. I have also ported eLua to it http://www.eluaproject.net @Jack: If you like I can also present the project in the GadgetFactory blog. Regards Thomas
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  4. Excellent. Now, we should document that somewhere... just unsure where. The code size different is substantial I believe, even if you don't actually use writes. Alvie
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  5. BTW, here is the official definition of drive strength, straight from the horse's mouth: https://www.xilinx.com/support/answers/38820.html "The drive strength of an I/O specifies how much current we can drive and sink while maintaining the minimum Voh and Vol levels." The bold part is the catch: it doesn't refer to the short circuit current.
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  6. Hi Jack, Sorry for the delay. Attached is the file. Thanks, fpga_guy top.bit
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  7. It should be fixed by now, I think.
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  8. I believe that's the wrong pin [in reference to a question about the clock input, and pin P55, that has been edited out I think]. The Papilio DUO generic UCF file has the following: NET CLK LOC="P94" | IOSTANDARD=LVTTL; TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%; See also http://forum.gadgetfactory.net/index.php?/files/file/235-papilio-duo-generic-ucf/. P55 seems to be one of the external pins on the board. Generally finding out what pins map to what, I rely on the published UCF files from this site, and then if there's a confusion I refer to the schematic. Note that there is more than one set of pin numbers (FPGA, and board) and more than one kind of thing termed "clock" (SPI bus clock signal for example). I don't see the references that identify P55 as clock or P38 as reset.
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  9. Yes. You can create designs using the standard Xilinx ISE and VHDL or Verilog.
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  10. check out papilio loader http://papilio.cc/index.php?n=Papilio.PapilioLoaderV2 i think thats the latest. if you have problems, search the forum for papilio loader assumes that you know how to use xilinx ise, et al. // F
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  11. Well, they wanted to plug that possibility so if you install Vivado then they also update the Digilent plugin You can however revert to the ISE version by going to (assuming 64-bit Windows) C:\Xilinx\14.7\ISE_DS\common\bin\nt64\digilent and run install_digilent.exe It will prompt if you want to "downgrade" the plugin.
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  12. Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
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  13. Here's my first motherboard submission to the gadgetbox project: GadgetBox-Propeller. This uses the Propeller CPU which is a custom 8-core CPU designed by Parallax. All of the GPIO pins are the same, so this was fairly easy to lay out. CPU product page Known things to do at this point: Add GPIO pin labels Validate serial programming eCog graphics
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  14. The problem above is related to bugs in JaWi's SUMP client, not the FPGA board. When the pulldown menu says 6 kB capture it really means 6 kS, i.e. it's the number of samples not the number of bytes. But then in the time calculation he incorrectly scales the resulting time by the number of channel groups. 6 kS at say 1 MS/s will always take the same time (in this case about 6 msec) independent of how many channel groups are enabled. If you try to select 12 kB or 24 kB samples (really 12 kS or 24 kS) with all four channel groups enabled then the memory is not enough so the error message is correct. As an alternative to Jack's Sump Logic Analyzer bit files for Papilio One 250k/500k you could try one of the bit files here: http://www.saanlima.com/download/Papilio_One/ , they are generated from the current Open Bench Logic Sniffer Verilog source files. Cheers, Magnus
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  15. Hi, did you notice that the Spartan 3 project you're trying to convert to Spartan 6 has been originally converted from a Spartan 6 project? See the link... "DCM" is just another word for this: >> - In ISE, select "Tools" then "Core generator" in the menu (note: the available selections may vary, depending on where you are in your project) >> - Go to "FPGA features", "clocking", "clocking wizard".
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  16. BTW, here is a link to a complete project using Microblaze_MCS: http://www.saanlima.com/download/pipistrello-v2.0/waveplayer_complete.zip The folder ise has has a complete xilinx project to build the hardware platform, including all the rtl files needed (the processor and all the custom I/O modules). The folder arduino-1.5.2-mcs contains the complete arduino environment for Windows with added microblaze support, including the gcc compiler and core arduino code for the microblaze hardware platform. The file waveplayer.ino is an arduino sketch for this system that plays wave files stored on a sd-card. It uses standard arduino libraries for SPI and sd-card support. Magnus
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  17. This is a quite complex undertaking and I'm not sure a forum post can explain all the aspects of doing a Arduino port for a different processor but I will try to give you a few hints on how to do this. 1) You need to create the hardware platform so that you can support the basic Arduino system, i.e. processor, memory, timer, digital I/O with optional PWM, uarts, SPI controller etc. The nice thing with creating your own I/O modules is that you can make them so that the porting of the Arduino core code is easier than if you use the Xilinx IP or other open-source I/O modules. For instance, if you make the SPI controller work the same as the AVR SPI controller (same registers and control bits) then you can use the already available SPI library with minimal modifications. 2) You need to understand the Arduino build system and create the necessary files and folders to support a new processor. The added files and folders will go in the <Arduino>/hardware folder. You can see how they added support for the ARM processor (i.e. sam) and create the same structure for microblaze. Part of this will be to port the core arduino code to your hardware platform and create the files platform.txt and boards.txt that will control how the build is done. This is the hard part of doing the port. The gcc compiler will be in the <Arduino>/hardware/tools directory. 3) For bootloader there are several possibility. One is to have bootloader code resident on the hardware platform that talks to a bootloader running on the development system (Linux or Windows) like how the did it for ZPUino (this mimics the Arduino way of loading code). Another alternative is to use the data2mem program and merge in the generated arduino sketch code directly to the bit file and download the resulting bitfile using JTAG (no bootloader needed but only works if the system memory is in BRAM). A third alternative is the store the arduino sketch code in elf format in the flash memory after the bit file and have an elf loader resident on the hardware platform that will load the elf code from flash to main memory and execute it (works for both BRAM and external memory). I have implemented the last two options for my systems. For Vivado, mb-gcc can be found in the Xilinx SDK directory. On my Windows install it can be found at C:/Xilinx/SDK/2015.3/gnu/microblaze/nt. I have not installed Vivado on my Ubuntu system so I can't say the exact path but my guess would be /opt/Xilinx/2015.3/SDK/gnu/microblaze/lin64 or something like that. Hope this helps.
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  18. Thanks Jack! It would be an honor to see this on the Gadget Factory blog. This project was quite suitable for the Duo, since it makes use of the AVR chip for some of the basic math and input controls processing, and leaves the hard stuff to the FPGA. Also, hats off to Hamster, whose own Mandelbrot project were the inspiration for this. My project was not a copy of his (after all, my objective here was to learn), but I did learn quite a bit from his implementation on how to pipeline a project like this. I posted a few other details on the project on the YouTube post, but I suspect some of the readers here would be more interested. Here is the bullet point description: • The Atmega32U4 is used to process the analog joystick, buttons, and rotary encoder to set the cursor position, zoom, and color map. This information is sent over to the FPGA via an SPI interface. • The FPGA runs the 800x600 pixel fractal calculations at 200 MHz using the onboard DSP48s. • The fractals are saved to SRAM, with each pixel stored as a 1 byte word. • A set of selectable 12-bit color maps are stored using the FPGA BRAM. I currently have over a dozen, and am planning on adding more color maps. • An 800x600 pixel SVGA controller on the FPGA is used to send a 12-bit color image to the LCD. I used the snap-off VGA wing from the LogicStart Shield. The LCD was an inexpensive 7” screen purchased off eBay, typically used for Raspberry Pi projects. • The case for this design was 3D printed, and custom designed just for this project. Finally, the 3D case could be easily modified for a more general purpose Papilio Arcade. The Papilio Duo drops right into it. Perhaps I'll post the SketchUp file on Thingiverse if there is interest.
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  19. And we were able to do a full simulation of the system, so we can find bugs on it.
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  20. it works. Using this Source and the Device source: http://www.macronix.com/Lists/ApplicationNote/Attachments/1148/AN0245V2%20-%20Using%20Macronix%20Serial%20Flash%20with%20Xilinx%20iMPACT%20Tools.pdf part: N25Q64
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  21. Filip

    Quadrature Decoder

    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
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  22. Latest code for windows and linux32 can be found here: http://pipistrello.saanlima.com/index.php?title=Arduino-1.5.2_on_Pipistrello
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