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Showing most liked content since 10/19/2016 in all areas

  1. 2 points
    Hi all, over the last half year I have implemented a processor and surrounding SoC bringing the RISC-V ISA (http://riscv.org) to the Papilio Pro. It implements the 32Bit integer subset (RV32IM). The project is hosted on Gitub (https://github.com/bonfireprocessor). It still needs some additional documentation, cleanup and ready-to-run ISE projects to make it easy reproducable for others. But I post this link now, to find out if anybody is interested in my work. I will soon also post a bitstream here so anybody with access to a Papilio Pro can play with it. I have also ported eLua to it http://www.eluaproject.net @Jack: If you like I can also present the project in the GadgetFactory blog. Regards Thomas
  2. 2 points
    Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
  3. 1 point
    Hello, I am using DesignLab 1.0.8 under Linux and I have a small problem when generating new bit files. The problem is that the case of the files is different from the default and therefore the IDE won't flash my new file. I either need to rename the file or create a symlink. For example the Multiple_Serial_Ports example Creates a Papilio_Pro.bit file while the IDE expects papilio_pro.bit. With kind regards
  4. 1 point
    I have used SK Pang Electronics (skpang.co.uk) which is a company based in the UK. I just checked and they have the Papilio Pro and Duo in stock. They are out of stock of other items. I noticed that prices rose significantly around the time of the Brexit result, and the fall of the UK pound against the dollar and other currencies. Then again you will get a better rate with the euro against the pound, which will offset for you. Buy now while the UK is still in the EU :-) good luck... --Gary
  5. 1 point
    The libraries are a fantastic aspect of the Arduino and the key thing that makes it a worthwhile if otherwise rather flawed platform. It took me a long time to warm up to Arduino but I love the way I can grab some widget and very often grab a library with example code to make it do something right away. It provides a great way to test the thing out and explore its capabilities right off the bat. I'd love to see a similar collection of HDL modules form, blocks of code that do the grunt work like initializing the device and communicating via whatever interface it uses and bring the controls out to sensible interfaces that can be tied into other modules in the top level file. Ideally these modules should be well commented, especially at the top level explaining what all the inputs and outputs do and what sort of signals they expect.
  6. 1 point
    Hmmm... the old Papilios use the FT2232D USB chip, the newer ones (e.g. Papilio Pro) the FT2232H high speed variant. With a more recent board, uploads "should" be fast. I'm using high speed (30 MHz, clock divider 0) JTAG with the -H chip routinely. For xc3sprog, it may be enough to write cables.txt via command line option, then edit the clock rate. I think I've done that once and got upload times (but probably for a compressed bitstream) 200 ms or so.
  7. 1 point
    Another update. I've now returned to Mike Field's original design, and done some work to port this to the Papilio Duo + Classic Computing shield. The main difference from the Papilio Plus is the memory is 512KBx8 rather than 256KBx16. This entailed a re-write of the memory controller to deal with half the memory bandwidth, but nothing else. I also added in the colour maps from Larry's Mandelbrot-Explorer. This is working very nicely indeed, panning is super smooth, and multiple colour maps is really funky. The picture below doesn't really do it justice! If anyone want to try this out, the source is it github, and I'm happy to post a .bit file on request: https://github.com/hoglet67/DSPFract Dave
  8. 1 point
    Update: I decided to try a newer Arduino library for the Wii chuck and a test sketch to read the buttons and joystick position and surprisingly it worked perfectly. I then took a Digilent Analog Discovery and used the Waveforms software to have a look at what was happening on the I2C bus on the working Arduino example and then the non-working DesignLab example on the Papilio and I could see a difference in the initialization sequence being sent from each. I guess I should have compared the two libraries and found the issue without breaking out a scope, but where's the fun in that, right? The Arduino example was sending hF0, h55, hFB, h00 as the init sequence. The Papilio example was sending h40, h00, hFB, h00 as the init sequence. After doing a bit more reseearch I changed the following section in the WiiChuck.cpp in the WiiChuck library in DesignLab as below: int WIIChuck_class::init_nunchuck() { int err = 0; if (I2C.start(WIICHUCK_ADDRESS,0)!=0) err = -1; if (err==0) // if (I2C.tx(0x40)!=0) - this is for OEM Wii nunchucks if (I2C.tx(0xF0)!=0) // for clone Wii nunchucks err = -1; if (err==0) // if (I2C.tx(0x00)!=0) - this is for OEM Wii nunchucks if (I2C.tx(0x55)!=0) // for clone Wii nunchucks err = -1; I2C.stop(); I recompiled the sketch, uploaded to the Papilio and I'm now getting the following results when testing: No Joystick or button activity - Chuck: 128 127 buttons 0 0 Joystick left - Chuck: 46 127 buttons 0 0 Joystick right - Chuck: 255 127 buttons 0 0 Joystick up - Chuck: 128 255 buttons 0 0 Joystick down - Chuck: 128 46 buttons 0 0 Button C - Chuck: 128 127 buttons 0 1 Button Z - Chuck: 128 127 buttons 1 1 Button C+Z - Chuck: 128 127 buttons 1 0 I was not aware that some (all?) clone chucks do not respond properly to the standard init sequence. The following comment was in the Arduino library that I used (https://playground.arduino.cc/Main/WiiChuckClass): // instead of the common 0x40 -> 0x00 initialization, we // use 0xF0 -> 0x55 followed by 0xFB -> 0x00. // this lets us use 3rd party nunchucks (like cheap $4 ebay ones) // while still letting us use official oness. // only side effect is that we no longer need to decode bytes in _nunchuk_decode_byte // seehttp://forum.arduino.cc/index.php?topic=45924#msg333160 Thanks for the advice Alvie, using the scope certainly revealed the issue even if it wasn't due to a hardware fault or misconfiguration. Regards, Anthony
  9. 1 point
    Hello, I've just returned from DConf 2017, in Berlin. There I gave a talk on how to use an extension of the D programming language (DHDL) to design hardware. I showed a demo of Classic Empire, a game written by Walter Bright (the original creator of D), running on a Papilio Pro, inside a soft-core RISC-V CPU, plus my own handmade "wing" IO accessories and respective controller IP blocks (VGA, 7-segment, sound, etc.). You can see a quick demo below: You can also see the full talk, if it sparks your interest: Thanks to the generosity of GadgetFactory, we raffled a Papilio Pro and some accessories to the participants of the talk: Gauging from his reaction, Vang Le was very surprised and happy to be the winner, and he's looking forward to exploring the world of FPGAs. In my demo I loaded the binary code for the game through the USB/UART, using a custom utility. In the next few months I plan to further tweak this demo, so that the game code is loaded from flash and it works with standard GadgetFactory wings. When that is done, I'll provide the bit stream files for the combined hardware design + the game. Walter Bright has indicated that he would provide permission for the FPGA version of the game to be distributed freely, so GadgetFactory could use it for its showcase. Later, I will provide the source code for my whole setup; I used the LDC 2 D compiler with the (old) LLVM RISC-V backend, and I had to workaround a lot of bugs of invalid RISC-V code. When the new LLVM RISC-V backend is released I expect all of that to be alleviated or completely fixed, which will help with the release of the complete demo setup. I'll keep providing updates and feedback here on the GadgetFactory forums. You can also follow me on Twitter (@Luis3m), or email me if you have any questions (http://www.luismarques.eu/about). Also, a shout-out goes to Mike Field, whose book / tutorial helped me get started with FPGAs and hardware design. I shared the love for his book with some conference participants :-) So long, Luís
  10. 1 point
    Excellent. Now, we should document that somewhere... just unsure where. The code size different is substantial I believe, even if you don't actually use writes. Alvie
  11. 1 point
    BTW, here is the official definition of drive strength, straight from the horse's mouth: https://www.xilinx.com/support/answers/38820.html "The drive strength of an I/O specifies how much current we can drive and sink while maintaining the minimum Voh and Vol levels." The bold part is the catch: it doesn't refer to the short circuit current.
  12. 1 point
    Hi Jack, Sorry for the delay. Attached is the file. Thanks, fpga_guy top.bit
  13. 1 point
    It should be fixed by now, I think.
  14. 1 point
    I believe that's the wrong pin [in reference to a question about the clock input, and pin P55, that has been edited out I think]. The Papilio DUO generic UCF file has the following: NET CLK LOC="P94" | IOSTANDARD=LVTTL; TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%; See also http://forum.gadgetfactory.net/index.php?/files/file/235-papilio-duo-generic-ucf/. P55 seems to be one of the external pins on the board. Generally finding out what pins map to what, I rely on the published UCF files from this site, and then if there's a confusion I refer to the schematic. Note that there is more than one set of pin numbers (FPGA, and board) and more than one kind of thing termed "clock" (SPI bus clock signal for example). I don't see the references that identify P55 as clock or P38 as reset.
  15. 1 point
    Yes. You can create designs using the standard Xilinx ISE and VHDL or Verilog.
  16. 1 point
    check out papilio loader http://papilio.cc/index.php?n=Papilio.PapilioLoaderV2 i think thats the latest. if you have problems, search the forum for papilio loader assumes that you know how to use xilinx ise, et al. // F
  17. 1 point
    Well, they wanted to plug that possibility so if you install Vivado then they also update the Digilent plugin You can however revert to the ISE version by going to (assuming 64-bit Windows) C:\Xilinx\14.7\ISE_DS\common\bin\nt64\digilent and run install_digilent.exe It will prompt if you want to "downgrade" the plugin.
  18. 1 point
    Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
  19. 1 point
    Here's my first motherboard submission to the gadgetbox project: GadgetBox-Propeller. This uses the Propeller CPU which is a custom 8-core CPU designed by Parallax. All of the GPIO pins are the same, so this was fairly easy to lay out. CPU product page Known things to do at this point: Add GPIO pin labels Validate serial programming eCog graphics
  20. 1 point
    The problem above is related to bugs in JaWi's SUMP client, not the FPGA board. When the pulldown menu says 6 kB capture it really means 6 kS, i.e. it's the number of samples not the number of bytes. But then in the time calculation he incorrectly scales the resulting time by the number of channel groups. 6 kS at say 1 MS/s will always take the same time (in this case about 6 msec) independent of how many channel groups are enabled. If you try to select 12 kB or 24 kB samples (really 12 kS or 24 kS) with all four channel groups enabled then the memory is not enough so the error message is correct. As an alternative to Jack's Sump Logic Analyzer bit files for Papilio One 250k/500k you could try one of the bit files here: http://www.saanlima.com/download/Papilio_One/ , they are generated from the current Open Bench Logic Sniffer Verilog source files. Cheers, Magnus
  21. 1 point
    And we were able to do a full simulation of the system, so we can find bugs on it.
  22. 1 point
    it works. Using this Source and the Device source: http://www.macronix.com/Lists/ApplicationNote/Attachments/1148/AN0245V2%20-%20Using%20Macronix%20Serial%20Flash%20with%20Xilinx%20iMPACT%20Tools.pdf part: N25Q64
  23. 1 point
    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
  24. 1 point
    Assuming the need to go to multi-layer for the BGA part, that looks like it will be a very expensive board. You might look at a part such as the XC3S500E-4PQG208I which is in a 208 pin PQFP package. The FPGA is a bit more expensive but the PCB will be a fraction the cost if you can keep it to 2 layers. Also at least when it comes to Seeed, the cost of the board increases rapidly with size. 5cm * 5cm max is around $1/bd, 10cm * 10cm max is $2.50/bd, while the next size up, 15cm * 15cm max is close to $9/bd. If you can manage to keep it within 10cm square then the bare boards are ridiculously cheap.