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  1. Hi everyone. Last year I wrote a Z80-based retro microcomputer which runs in the Papilio Pro. It started out small but I added a few interesting features, in particular a memory management unit and a 16KB cache to hide the SDRAM latency. I've ported several operating systems to it. Both the hardware and software aspects of the project have been good fun with lots of new opportunities to learn. I've just made my first public release, you can download it at http://sowerbutts.com/socz80/ and try it out. That page also describes the project in a bit more detail. RAM disk images are included to boot CP/M-2.2, MP/M-II and UZI (a UNIX system). I've included Zork and the Hitchhiker's Guide game which will play under all three operating systems; they are native CP/M application but MP/M-II implements the CP/M system calls, and UZI includes a CP/M emulator. The release also includes the full VHDL source code for the machine and the source code to all the software I've written, with the exception of the UZI port which I plan to release shortly after I extend it to support the N8VEM Mark IV SBC. Please let me know if you get it to work! This post has been promoted to an article
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  2. Hmm, this is something I started myself a while ago. One of the problems with extending the AVR softcore is that it just didn't seem to be built for a peripheral rich setup (IO space, etc). But I didn't want to leave an open source GCC based solution. Which is why I've watched the ZPU work with interest. I recently tried to use a quadrature interface from opencores, but it was far too featureful and resource heavy. So instead, I created my own "simple" quadrature interface for the ZPU, and using the standard HD44780 code in the ZPUino IDE install, created a sketch to read the quad counter and write to the LCD. It is so very nice to read a quadrature encoder as simply as: unsigned int y=REGISTER ( IO_SLOT (8) ,0); Serial.println(y); And to know that it is being clocked at 96Mhz. (Of course, I most probably have created a piece of junk, full of bugs - but I think it's cute) The code's a complete mess, but if you're interested... it's attached. View attachment: ZpuQuadDec.zip
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  3. Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
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  4. Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
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  5. Or any other Xilinx FPGA board with an FTDI chip with MPSSE-engine connected to the JTAG pins (like Pipistrello but not Mojo or Saturn). This is using the xilinx virtual cable driver. Playtag is written by Patrick Maupin. Steps: 1) you need python 2.7 installed. Get it here:http://www.python.org/getit/ 2) unzip the attached zip file playtag.zip somewhere on your computer 3) open a cmd-window and cd to <playtag>\tools\jtag 4) connect your Papilo board to the computer 5) type xilinx_xvc.py ftdi, this will report the available FTDI ports.You should see the A and B ports of the Papilio board (see image). 6) type xilinx_xvc.py ftdi 0, this will start the xilinx virtual cable server on the A port of the Papilo board 7) you can now use impact and chipscope etc. by selecting the xilinx_xvc plugin. Use this plugin settings: xilinx_xvc host=localhost:2542 disableversioncheck=true See attached images and zip file. Do a google-search for xilinx_xvc for more info on how to use the virtual cable driver. Magnus playtag.zip
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  6. I have the J1 CPU running on the Papilio Duo. It runs a standard 32-bit ANS Forth, communication is through the UART. It is working quite well; in fact I used it to run my slides for a presentation last week (slides were on microSD, buttons and VGA output from the Computing Shield). Is anyone interested in giving it a tryout? Let me know if so and I will put together a release. Thanks! J.
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  7. Filip

    Quadrature Decoder

    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
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  8. Once you get it gojng, rather than using a sine wave, why not try a GPS gold code? ( or something similar to one) It is a pseudo random bit stream that is quite long. When you correlate with an external signal you can get a really precise phase lock. This time to phase lock is what gives the long time to first fix of a GPS as it trys all the different alignments, but once locked it is very solid, even though the power levels of the signal is well below the noise floor and mixed up with all the other GPS birds. By having g a real time clock on the GPS the time to first fix is improved as the GPS knows where to start hunting. Also, I believe that most GPS units have a one bit DAC, so maybe a bandpass filter and to compare against the long term average is all you need?
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  9. I had a copy of Lady Bug written by Arnim Laeuger, that I downloaded from fpgaarcade a long long time ago and forgot all about it. I recently came across it and I spent a little time getting it going for the Papilio. Unfortunately it won't fit on a Papilio One, it uses about 28 BRAMs and the Papilio One doesn't have any external memory and not enough internal memory. Good news is, it will fit entirely into a Papilio Pro or any Spartan 6 FPGA without needing any external RAM or ROM. Getting this ported to the Papilio was just a matter of writing a top level module to connect the ladybug machine to the various ROMs and input controls. This is the first time I've finally used a PS2 keyboard controller from here which appears to have a well written bidirectional PS2 controller. Bidirectional means that when you hit for example the caps lock key, the PS2 controller detects that and sends data back to the keyboard to turn on the caps lock LED. The key mapping I chose can be easily changed if you look in the source code and have a handy PS2 key code reference. As is, the game should be playable with the arrow keys. A small issue, if you have your monitor tilted one way to get other games like Pacman showing correctly, then Ladybug will appear upside down. If you can tilt the monitor the other way, you're all set, if however you can't and just reverse the state of the flip_screen_g variable, the screen will appear at first glance to be correctly flipped but unfortunately only the background is flipped, the sprites and key mapping are not, so, for example, Ladybug will appear to move the wrong way, won't line up with the corridors, eating the dots on one side of the screen causes the dots on the opposite side to disappear, etc. Currently three games are supported: Ladybug, Dorodon (a Ladybug like clone) and Cosmic Avenger (a Defender like clone). I haven't searched what other ROMs the original hardware supported, if any. The source code is available here. To make it all work, download the source then download and place the game ROMs into the appropriate ROMs folder. See the readme file in each folder for a list of the files and checksums you should be looking for, If you're on Windows, run the make_roms batch file in the relevant game rom folder. Game ROMs will be converted to vhdl files in the build directory. If you're on linux, there appears to be a makefile based system for creating ROMs and other files in the hex folder, seemed to work for me in MinGW, but I use Windows primarily. Once the ROM files are converted to VHDL, run the ladybug_papilio.xise project in the top directory and synthesize then upload to your board. You need a Papilio Pro with a Arcade Megawing and a PS2 keyboard in port "PS/2 B", VGA and audio connected. Enjoy! This post has been promoted to an article
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  10. There is plenty wrong with VHDL and Verilog but I have to say the biggest problem I (and I think many people from a programming background) have is the business of thinking in parallel. Not just the idea that things like assignments take time and aren't instant but things like the fact that (except for power in some cases) it's actually not worth doing conditional evaluation of something, you can evaluate it every clock at no extra cost, in fact you can evaluate hundreds of un-needed things for free just in case they are relevant to a given cycle. Not sure a language can help much with that. There is simply a gap between the conceptual model of programming and the reality of FPGA.
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  11. Hi, not every pin can function as clock input. See here http://www.xilinx.com/support/documentation/user_guides/ug385.pdf page 30, search for "GCLK" in the name. Now did you know that there are PLLs inside the FPGA? It takes 2 min of work (maybe a bit more if you do it the first time) to run the core generator and turn the existing 32M clock into 20 MHz or whatever you like. It's one of the most useful features, IMO, in everyday use.
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  12. ever heard of "paralysis by analysis"? My advice still stands: Don't try to buy the "best" or the "right" board. Just get any cheap board, spend two working weeks and learn to make that LED blink.
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  13. Well after finishing this mini project I was very sad because the Double Dragon only has a handful of (not really that great) songs it can play over the YM2151 chip. I started looking around "teh nets" for more YM2151 music and eventually I arrived in Japan so to speak. I guess since Yamaha is a Japanese company it makes sense that it was adopted as the chip of choice on local computer systems. One such very popular system is the Sharp X68000 which as the name suggests, is based on a 68000 CPU. The cool thing about this system is that it has vast amounts of music created for it, here is a hard disk image with over thirty thousand music files on it. The music is in an MML (Music Macro Language) format and typically has an extension of .MDX In fact there are two types of files, .MDX and .PDX and after a fair amount of looking into these formats it turns out that while the MDX files are the Music Macro files, the PDX files contains sampled sounds that can accompany the melodies produced via FM modulation through the MDX files. In fact the PDX files contain 4 bit ADPCM data and they could be directly feed into a chip such as the MSM5205. Another cool thing is that some very nice people have written and open sourced an MML parser that can read MDX/PDX file combos and play them via a software implementation of the YM2151 chip and some generic ADPCM decoder. It is at this point that my other post comes in. With such vast amounts of YM2151 music it was only fair to find a way to play them, so I took the source of the MML player and carved out the software YM2151 implementation (which was in fact copied from MAME's implementation of the YM2151) and only left the calls to initialize the chip and write to the registers. I then had the initialization call simply pulse the reset line to the chip while the write register calls the FTDI functions to transfer the register data to the FPGA which in turn writes it to the real chip. The result can be seen in this 4 minute video. Hope you enjoy it! If the embedded video shows in portrait mode (tall and narrow) click on the youtube logo in the bottom right corner of the video and it will show properly in landscape mode.
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  14. Hi, I've got my SDRAM controller up and running on the Papilio Pro as well as the Logi-Pi. http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller It is running at 96MHz, but as it currently does the full "row open, read or write two words, close row" cycle for every memory access it isn't too fast. However, 24MB/s is more than fast enough if you have any audio projects in mind... flanger, delay, chorus, reverb etc Maybe somebody will write a nice roomy reverb for on the RetroCade?? 8MB is enough for 43 seconds of 48k/16bit audio. That gets you an awful lot of reverb!
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  15. I decided to also port the Demon 3.07 verilog code to Papilio_One. This version is identical to the code running on the OpenBench Logic Sniffer board except for using 32MHz oscillator and using serial@115200 instead of SPI. It supports both meta data and input pin data query. The full XISE project can be found here: http://www.saanlima.com/download/Papilio_One/Papilio_One_OLS_3.07.zip 250K and 500K bit files are attached. Let me know if you notice any strange behavior. This post has been promoted to an articlelogic_sniffer_P1_250K.bit logic_sniffer_P1_500K.bit
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  16. A friend of mine found a junked Hitachi LCD and gave it to me to see if I could get it going. The LCD is an older type, monochrome low resolution. I couldn't find a datasheet for it or pinouts so I went old school and tracked down datasheets for the chips on board and did some reverse engineering of the schematic using a continuity meter. A very good datasheet resource is the "Hitachi LCD Controller Driver LSI Data Book" which is a compendium of a large number of Hitachi LCD controller chips. According to the datasheet, the large chips on board are six HD61200 column shifters (IC3,4,5 and IC 6,7,8) and two HD61203 row shifters (IC 1,2). The unpopulated footprint is is a little weird with some missing pin traces (the one trace gaps on the short edge of the chip) and one less pin on one side of the chip compared to the other side. This footprint matched exactly the footprint of the HD61830 controller chip. The last unpopulated footprint of IC12 should be a SRAM chip for the IC11 controller. The LCD has one 20 pin set of connections that just go to the unpopulated IC11 controller chip. It also has a 10 pin edge connector that connects to the outputs of the IC11 controller and the inputs of the row/column shifters. It appears the PCB was designed to work in both a smart mode (with controller) and a dumb mode (no controller) hence the two different connector options. Because the controller chip was missing, I realised immediately that this LCD could not be driven in a static mode, where you just write data to the LCD internal memory and you can leave it alone to display that data. Instead this LCD would be more like a VGA display where you must constantly send data to it to refresh the picture. The 10 pin connector pinout is:1 to pin 47 IC11 D1 - pin 42 (DR) IC 3,4,5 (upper half of screen)2 to pin 10 IC11 FLM - pin 50 (DR) IC 1,23 to pin 5 IC11 MB - no connection4 to pin 11 IC11 CL1 - pin 52 (CL2) IC 1,2 and pin 37 (CL1) IC 3,4,5,6,7,85 to pin 46 IC11 CL2 - pin 40 (CL2) IC 3,4,5,6,7,86 to pin 48 IC11 D2 - pin 41 (DL) IC 6,7,8 (lower half of screen)7 to pin 29 IC11 VCC (+5V supply)8 to pin 20 IC11 GND9 to TR1 Collector (LCD bias -10V )10 to TR1 Base (LCD bias enable, contrast?) The internal chip to chip connections of the column shifters match those from the datasheet as below. Essentially each column shifter can address 80 columns and three of them are chained together to form a 240 column shifter. There is one set for addressing the top half of the screen and another set for the bottom half of the screen. The two row shifters IC1 and IC2 then select one of the 64 rows to be addressed. Together these two chips can address 128 rows but because their inputs are connected together they address the entire screen (both top and bottom of screen simultaneously) so the entire screen is refreshed in 64 cycles. In cycle 1, row 1 and row 65 are selected and a line is drawn through the top and bottom column shifters, in cycle two row 2 and row 66 is selected, etc, through to cycle 64 where row 64 and row 128 are selected. So the LCD has a resolution of 240x128 but can be throught of as two independent 240x64 areas stacked together. Input D1 sends serial pixel data to the top half of the LCD (top column shifters) and D2 to the bottom. CL2 is the LCD master clock which can go up to 2.5Mhz according to the datasheet. CL1 is the signal that latches data from the shifter outputs to the display registers, MB pin is not connected to anything and FLM is the input to the row shifters. At the start of each frame a 1 is shifted into the row shifters through FLM then zeroes are shifted for the remaining 63 cycles. This way a single bit travels through the both top 64 and bottom 64 rows selecting one row at a time in each half of the screen. Once I understood the basic function of the shifters I decided to hook it up the a Papilio One FPGA as the ideal driver hardware. Please note that the LCD panel runs off 5V whereas the FPGA outputs are 3.3V, however since the LCD does not output signals to the FPGA, it is quite safe to drive the 5V LCD inputs with 3.3V from the FPGA without using level translators. I decided to display a picture on the LCD and I picked a dithered bilevel picure of Lena. I cropped it to 256x128 resolution so it can be easily stored and displayed to the LCD without performing additional math. If I had stored the picture in its more compact 240x128 native LCD resolution I'd have to convert the LCD vertical and horizontal coordinates to ROM addresses via some math such as address = v + h*240 whereas by storing the picture as two ROMs of 256x64 bytes the v counter can directly index ROM address lines 10..5, the top bits of the h counter can index ROM address lines 4..0 and the bottom three bits of the h counter index a bit within the currently addressed ROM byte. The top half 256x64 of the 256x128 picture is stored into one 8x2K RAMB and the bottom 256x64 of the picture into another 8x2K RAMB. The reason for using two separate RAMBs is because the top and bottom of the image is shifted simultaneously so both RAMBs need to be accessed simultaneously. Another way of doing this would be to create a 16x2K memory and use 8 bits for the top and 8 bits for the bottom, or a 8x4K using 4 bits for top, 4 bits for bottom but any of these schemes would require the original image to be preprocessed and interlaced accordingly. The final code to drive the LCD ended up being very simple and is shown below. One last thing to mention is that initially I got no picture at all. After of course simulating the design to make sure the signals produced are correct and then examining the final design running on the FPGA with an oscilloscope, I saw that while the inputs to the chips had valid signals, all the outputs of the row and column drivers were sitting at 5V instead of toggling. After refering to the datasheet again I realised that these drivers need a negative Vee voltage in the range -7v to -17v. This would normally be connected to the collector of transistor TR1 and the base of TR1 could adjust the amount of voltage let through the transistor forming a contrast adjustment. Since I didn't have a handy negative supply I simply soldered a 9V battery in reverse, with the positive to the system ground and the negative directly to the Vee (emitter of TR1). This then provided the necessary negative bias to allow the LCD to display a picture. The contrast is fairly low due to the 9V battery not supplying the ideal bias voltage, I guess -12V would have been better. -- Driver for LCD type LMG6351PLYR, 240x128 resolution, monochromelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;library unisim; use unisim.vcomponents.all;entity lcd_top isport ( RST_I : in std_logic; -- active high reset CLK_I : in std_logic; -- master clock -- D1_O : out std_logic; -- data to top half of lcd column shifter D2_O : out std_logic; -- data to bottom half of lcd column shifter CL1_O : out std_logic; -- clock CL2_O : out std_logic; -- latch display data FLM_O : out std_logic; -- row drivers input MB_O : out std_logic -- not used);end;architecture RTL of lcd_top is signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal cl1 : std_logic := '0'; signal cl2 : std_logic := '0'; signal d1 : std_logic := '0'; signal d2 : std_logic := '0'; signal flm : std_logic := '0'; signal mb : std_logic := '0'; signal bits_top : std_logic_vector( 7 downto 0) := (others=>'0'); signal bits_bot : std_logic_vector( 7 downto 0) := (others=>'0'); signal mainctr : std_logic_vector( 3 downto 0) := (others=>'0'); signal hctr : std_logic_vector( 7 downto 0) := (others=>'0'); signal vctr : std_logic_vector( 5 downto 0) := (others=>'0');begin -- input assignments rst <= RST_I; clk <= CLK_I; -- output assignments FLM_O <= flm; CL1_O <= cl1 and (not cl2); CL2_O <= cl2; D1_O <= d1; D2_O <= d2; MB_O <= mb; -- divide main 32Mhz clock by 16 to get 2Mhz clock clk_inst : process(clk) begin if rising_edge(clk) then mainctr <= mainctr + 1; end if; end process; -- 2Mhz clock (max 2.5Mhz per datasheet) cl2 <= mainctr(3); -- horizontal counter hctr_inst : process(cl2, rst) begin if (rst = '1') then hctr <= (others=>'0'); elsif rising_edge(cl2) then if hctr = 239 then hctr <= (others=>'0'); else hctr <= hctr + 1; end if; end if; end process; -- vertical counter vctr_inst : process(cl2, rst) begin if (rst = '1') then vctr <= (others=>'0'); elsif rising_edge(cl2) then if vctr = 64 then vctr <= (others=>'0'); elsif hctr = 239 then vctr <= vctr + 1; else vctr <= vctr; end if; end if; end process; -- generate CL1 (display data latch) cl1_inst : process(cl2) begin if falling_edge(cl2) then if (hctr = 239) then cl1 <= '1'; else cl1 <= '0'; end if; end if; end process; -- generate FLM flm_inst : process(cl2) begin if falling_edge(cl2) then if (hctr = 239) and (vctr = 0) then flm <= '1'; else flm <= '0'; end if; end if; end process; -- image data shifters bit_inst : process(cl2) begin if rising_edge(cl2) then case hctr(2 downto 0) is when "000" => d1 <= bits_top(7); d2 <= bits_bot(7); when "001" => d1 <= bits_top(6); d2 <= bits_bot(6); when "010" => d1 <= bits_top(5); d2 <= bits_bot(5); when "011" => d1 <= bits_top(4); d2 <= bits_bot(4); when "100" => d1 <= bits_top(3); d2 <= bits_bot(3); when "101" => d1 <= bits_top(2); d2 <= bits_bot(2); when "110" => d1 <= bits_top(1); d2 <= bits_bot(1); when "111" => d1 <= bits_top(0); d2 <= bits_bot(0); when others => null; end case; end if; end process; -- top and bottom of screen image ROMs ROM_TOP : entity work.ROM_TOP port map ( CLK => clk, ENA => '1', ADDR (10 downto 5) => vctr, ADDR ( 4 downto 0) => hctr(7 downto 3), DATA => bits_top ); ROM_BOT : entity work.ROM_BOT port map ( CLK => clk, ENA => '1', ADDR (10 downto 5) => vctr, ADDR ( 4 downto 0) => hctr(7 downto 3), DATA => bits_bot );end RTL;
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  17. I've just finished my 8 digit frequency counter - I'm just waiting for a GPS module to arrive so I can use it as the reference timesource. Here's a block diagram of the project: And here is a photo of it in action, when using a one pulse per second generated from the local Xtal as the reference. Full source is up on my wiki at http://hamsterworks....equency_counter This post has been promoted to an article
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  18. 3 bit of green, 3 bit of red, and 2 bit of blue. http://en.wikipedia.org/wiki/8-bit_color
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  19. Hi all, over the last half year I have implemented a processor and surrounding SoC bringing the RISC-V ISA (http://riscv.org) to the Papilio Pro. It implements the 32Bit integer subset (RV32IM). The project is hosted on Gitub (https://github.com/bonfireprocessor). It still needs some additional documentation, cleanup and ready-to-run ISE projects to make it easy reproducable for others. But I post this link now, to find out if anybody is interested in my work. I will soon also post a bitstream here so anybody with access to a Papilio Pro can play with it. I have also ported eLua to it http://www.eluaproject.net @Jack: If you like I can also present the project in the GadgetFactory blog. Regards Thomas
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  20. BTW, here is the official definition of drive strength, straight from the horse's mouth: https://www.xilinx.com/support/answers/38820.html "The drive strength of an I/O specifies how much current we can drive and sink while maintaining the minimum Voh and Vol levels." The bold part is the catch: it doesn't refer to the short circuit current.
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  21. check out papilio loader http://papilio.cc/index.php?n=Papilio.PapilioLoaderV2 i think thats the latest. if you have problems, search the forum for papilio loader assumes that you know how to use xilinx ise, et al. // F
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  22. BTW, here is a link to a complete project using Microblaze_MCS: http://www.saanlima.com/download/pipistrello-v2.0/waveplayer_complete.zip The folder ise has has a complete xilinx project to build the hardware platform, including all the rtl files needed (the processor and all the custom I/O modules). The folder arduino-1.5.2-mcs contains the complete arduino environment for Windows with added microblaze support, including the gcc compiler and core arduino code for the microblaze hardware platform. The file waveplayer.ino is an arduino sketch for this system that plays wave files stored on a sd-card. It uses standard arduino libraries for SPI and sd-card support. Magnus
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  23. Thanks Jack! It would be an honor to see this on the Gadget Factory blog. This project was quite suitable for the Duo, since it makes use of the AVR chip for some of the basic math and input controls processing, and leaves the hard stuff to the FPGA. Also, hats off to Hamster, whose own Mandelbrot project were the inspiration for this. My project was not a copy of his (after all, my objective here was to learn), but I did learn quite a bit from his implementation on how to pipeline a project like this. I posted a few other details on the project on the YouTube post, but I suspect some of the readers here would be more interested. Here is the bullet point description: • The Atmega32U4 is used to process the analog joystick, buttons, and rotary encoder to set the cursor position, zoom, and color map. This information is sent over to the FPGA via an SPI interface. • The FPGA runs the 800x600 pixel fractal calculations at 200 MHz using the onboard DSP48s. • The fractals are saved to SRAM, with each pixel stored as a 1 byte word. • A set of selectable 12-bit color maps are stored using the FPGA BRAM. I currently have over a dozen, and am planning on adding more color maps. • An 800x600 pixel SVGA controller on the FPGA is used to send a 12-bit color image to the LCD. I used the snap-off VGA wing from the LogicStart Shield. The LCD was an inexpensive 7” screen purchased off eBay, typically used for Raspberry Pi projects. • The case for this design was 3D printed, and custom designed just for this project. Finally, the 3D case could be easily modified for a more general purpose Papilio Arcade. The Papilio Duo drops right into it. Perhaps I'll post the SketchUp file on Thingiverse if there is interest.
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  24. You will need to eventually filter those, and also do some clock domain crosssing. All depends on exactly what you want to do. Simulation and real-world differs a lot when the IO pins are used. Care to share more information ?
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  25. I don't have the code you referenced but I am assuming it is displaying a seven segment on vga. Maybe you are trying to connect the virtual seven segment lines to the vga lines. I believe the errors you are getting are because you are attempting to connect a std_logic_vector to a std_logic signal. If you are trying to connect a one bit vga signal to a three bit you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.
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  26. Hi Im new to FPGA but have one question: Concerning Commodore MOS chips Is there open source for: 1351 Mouse Controller C64/C128 Ram chips REC memory controller SID: 6581,6582,8580 last known revisions? The last item is: I have heard that CBM MOS chips could possibly be redone using xilinx using PLD but its difficult but would any of the Papilio code still work with Xilinx software? Is there any open source for anything like the CBM MOS 1351 controller chip. (1351 was CBM Mouse, worked in Joystick Mode and Proportional mode). Other controllers wont work because the 1351 somehow worked along with the SID Oscillator, without that it wouldn't work. I hope I asked this in the right forum so any help is appreciated. Thank you, Terry Raymond
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  27. Jack, I think there is a lot to like about the LinkSprite board. It would be a good base to start from. I certainly would like to help support this effort by buying some if you put them up in the store. FPGA modules ( Xilinx and Altera) would be a good place to start to expand the idea. Let us know how we can help! Bob
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  28. Jack I have used the standard Arduino PS2 library which I found here: http://playground.arduino.cc/ComponentLib/Ps2mouse The link to download the library is http://playground.arduino.cc/uploads/ComponentLib/ps2.zip Please note - that in the header file ps2.h you have to change WProgram.h" with "Arduino.h". I put the mouse into PS2/A and the keyboard into PS2/B You set up the pins with the following lines of code: PS2 mouse(5, 4); //PS2/A Mouse Clock = 5, Data = 4PS2 kbd(39, 41); //PS2/B Keyboard Clock = 39, Data = 41 Here's the simple test sketch #include <ps2.h>#define circuit Computing_Shieldunsigned int x_abs = 32767;unsigned int y_abs = 32767;int delta_x = 0;int delta_y = 0;/* * an arduino sketch to interface with a ps/2 mouse. * Also uses serial protocol to talk back to the host * and report what it finds. *//* * Pin 5 is the mouse data pin, pin 6 is the clock pin * Feel free to use whatever pins are convenient. */PS2 mouse(5, 4);PS2 kbd(39, 41);void kbd_init(){ char ack; kbd.write(0xff); // send reset code ack = kbd.read(); // byte, kbd does self test ack = kbd.read(); // another ack when self test is done}/* * initialize the mouse. Reset it, and place it into remote * mode, so we can get the encoder data on demand. */void mouse_init(){ mouse.write(0xff); // reset mouse.read(); // ack byte mouse.read(); // blank */ mouse.read(); // blank */ mouse.write(0xf0); // remote mode mouse.read(); // ack delayMicroseconds(100);}void setup(){ Serial.begin(115200); mouse_init(); kbd_init(); Serial.println("Starting"); }/* * get a reading from the mouse and report it back to the * host via the serial line. */void loop(){ char mstat; char mx; char my; unsigned char code; /* get a reading from the mouse */ mouse.write(0xeb); // give me data! mouse.read(); // ignore ack mstat = mouse.read(); // left button = 001, right = 010 mx = mouse.read(); my = mouse.read(); if(mx>=0 && mx <= 127) { delta_x = mx; } if(mx>=128 && mx <= 255) { delta_x = -(255 - mx); } if(my>=0 && my <= 127) { delta_y = my; } if(my>=128 && my <= 255) { delta_y = -(255 - my); } x_abs = x_abs +delta_x; y_abs = y_abs +delta_y; Serial.print(mstat, BIN); Serial.print(" "); Serial.print("\tX="); Serial.print(mx, DEC); Serial.print("\tY="); Serial.print(my, DEC); Serial.print("\dX="); Serial.print(delta_x, DEC); Serial.print("\dY="); Serial.print(delta_y, DEC); Serial.print(x_abs, DEC); Serial.print(" "); Serial.print(y_abs, DEC); Serial.println();// code = kbd.read(); // Serial.print(code, HEX); // Serial.print(" ");} My more complicated sketch can be found on github gists here https://gist.github.com/anonymous/892a097bc8bbbbf1c5ca regards Ken
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  30. This is not correct, the DUO does have a USB 2.0 chip on board (FTDI 2232H) and it can do up to 30 Mbits/sec in MPSSE mode and up to 12 Mbits/sec in serial mode. Not as fast as you want but faster than 3 Mb/sec. Magnus
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  31. (In the meantime, anyone using VMWare that can't boot DesignLab -- go into VMWare's sharing settings and turn off sharing. Sharing makes your Windows home folder read-only, which the Arduino version of java doesn't like when it's trying to enumerate the serial devices.)
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  32. Mine arrived err... Thursday? I can't even remember, I've been too busy playing with it to care. I dug a jumper out of a bits box and it works fine. Jack, you've done a wonderful job and my jaw hit the desk when I came across the documentation for the LogicStart Shield- so wonderfully thorough! Although the FPGA book has yet to be updated, it's easy enough to work through and I've started the early chapters again to get back up to speed. I can't wait to start talking to the FPGA from the AVR. All in all, a damned good turnout for a Kickstarter- everything arrived safe 'n' sound, everything works, thorough documentation, good support all round. The only thing I'm wanting for is more time to play with it!
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  33. That's the spot sorry not much help ATM but it's almost 10pm and I work very early tomorrow. I will reply back on wed after I have a chance to look into it.
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  34. Here's how to read a pot, using only two resistors and a capacitor: http://hamsterworks.co.nz/mediawiki/index.php/Cheap_Analogue_Input It is based around the technique used for the joystick interface on the Apple II. Only downside is that you need to calibrate the the limits - but perfect as a paddle interface for a game of Pong, where you could just remember the max & min readings.
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  35. you have Great video Channel on YouTube thank you very much wish you upload more video Tutorials about FPGA , VHDl , and Papilio in the Future MY REGARDS
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  36. Yeah the subscription is only $50/year for the electronic edition (pdf download). I've been reading CC since I was a young whipper snapper, I have a full pdf collection back to issue 1.
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  37. >> I was thinking it's easy to learn FPGA and then make your idea real by using it It is not. It is 1000x harder than it looks. You would use a "virtual com port", send serial data from PC to FPGA. This is relatively easy. Even easier, implement a pseudorandom generator to create the data. But, sorry for being direct, you're totally in over your head. Proposal: Why don't you buy some cheap low-end FPGA board. Papilio is fine, so is any other, just don't try to anticipate what you think you need. What you really need is one LED and two months hard work. Learn to make it blink, control it through the PC (USB-serial port and UART). When you can do that, you'll be in a much better position to judge the task at hand. It would be realistic for an experienced engineer but not if you're starting from square one. PS you don't actually have to buy it, just get the design tools and learn to use them (and get used to simulate: Hardware just tells you "it doesn't work". Not "why"). The tools are neither beginner- nor user friendly, takes a lot of patience.
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  38. One mini one micro at least avoids getting them the wrong way around
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  39. We're ultimating the ZPUino 2.0 release right now. Some of the most prominent changes include the new Arduino 1.5 IDE, and a few important changes in HDL code. One of the changes is support for device identification, which allows the user to scan the available devices using a product and vendor ID, like USB and PCI do. Here's a sample output from my "systeminfo" sketch, running on a PPro board: Press ENTER to show system infoSlot 0: ZPUino System ControllerSlot 1: ZPUino UARTSlot 2: ZPUino GPIO ControllerSlot 3: ZPUino Dual Timer Interface with PWMSlot 4: ZPUino SPI interfaceSlot 5: ZPUino 16-Bit Dual SigmaDeltaSlot 6: ZPUino SPI interfaceSlot 7: ZPUino Hardware CRC16 engineSlot 8: No device attachedSlot 9: No device attachedSlot 10: No device attachedSlot 11: No device attachedSlot 12: No device attachedSlot 13: No device attachedSlot 14: No device attachedSlot 15: ZPUino Bootloader CodePPS outputs: 6 PPS0 maps pin 0 of '16-Bit Dual SigmaDelta' in slot 5 PPS1 maps pin 0 of 'Dual Timer Interface with PWM' in slot 3 PPS2 maps pin 1 of 'Dual Timer Interface with PWM' in slot 3 PPS3 maps pin 0 of 'SPI interface' in slot 6 PPS4 maps pin 1 of 'SPI interface' in slot 6 PPS5 maps pin 1 of '16-Bit Dual SigmaDelta' in slot 5PPS inputs: 1 PPS0 maps pin 0 of 'SPI interface' in slot 6Not only the slot devices can be identified, but also their PPS indexes. This eases the development of libraries. In conjunction with this a few libraries will be published, including a "BaseDevice" from which you should derive your code classes that are to use wishbone devices, and specify your vendor/product IDs and the instance number. A "DeviceRegistry" class will be avaliable to control which devices are registered to which slots. All this will be properly documented before 2.0 release. Alvie
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  40. I've ordered a batch of PCB from Seeed (ETA 3 weeks). If anybody would like one (less the through-hole components) just drop us a line. The pins are laid out for the Adafruit Themocouple Amp/ADC board, but should work with andything. It also has four general purpose LEDs on it
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  41. FYI, there is now a 32-bit 5V-tolerant buffer wing available for Papilio and Pipistrello boards. The 32-bit I/O bus is divided into four groups of 8 with individual direction and enable control for each group. The wing is designed for use with the Open Bench Logic Sniffer code. See http://saanlima.com/store/index.php?route=product/product&product_id=55 for more info and schematic.
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  42. Well done Kosak, It is my hope that this forum will have more posts from people showcasing their projects step by step as they are developed covering both successes and failures, or showing their troubleshooting techniques. Then we can all pitch in with ideas. I attempted to do this with my latest Roboton posts, though given the lack of responses, perhaps it was too hard for people to follow or they may even have found the posts annoying and just skipped them 1) What I do for all my projects is create a special directory which I usually call "build" but any name will do. This directory can only be specified when creating a new project and I haven't found a way to change it through the GUI afterwards. If you already have created the project then open the .xise project file with a text editor and search for "working directory" which will contain just an empty string in quotes like so "", change that to "build" and save it. The next time you open the project it will ask you if you want to create this directory and answer yes. From now on, all the junk during the build will end up in this directory. I think there was a while ago a post or perhaps an article on the papilio page discussing this, The recommended way to create a project directory structure was along these lines: root / +-build +-doc +-source +-tools Where "build" is the directory I mentioned above, "doc" contains project documentation, datasheets, useful references, etc, "source" (or "src" or "hdl" if you prefer contain the HDL source code of your project then "tools" can contain useful scripts for building parts of your project such as binary to VHDL converters to create ROM files or any other scripts or executables needed for your project. 2) You're right, even if your case statemnt covers all possible cases, you still get a warning during synthesis unless you have an "others" case (durrr!). If you just need "others" as a filler that does nothing I usually use "when others => null;" 3) Nothing wrong with that. Usually you do this if you're going to re-use that piece of code several times, then you turn it into a separate module. You can now include that module file into other projects that need a hex to 7seg decoder. This post has been promoted to an article
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  43. On second thought I think that it really should say process(ready_q, clkrise, clkfall)begin if ready_q='0' and samprise = '0' and clkrise='1' then do_shift <= '1'; elsif ready_q='0' and samprise = '1' and clkfall = '1' then do_shift <= '1'; else do_shift<='0'; end if;end process;So that data is shifted on the opposite edge of the sampling edge... But I might be wrong..
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  44. Excellent nullobject. That will be helpful for many people out there.
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  45. Good evening Mr Hamster The project is very interesting. I am a student and if u Could you help me?. I want to send audio. You said, audio with 16-bit resolution high quality mono. 1221381325 + / - 1.000.000 but I don´t understood very well that I add audio input in the process.,and what signal I use. This would be: if beep_counter(19) = '1' then phase_accumulator <= phase_accumulator + 1222381325; else phase_accumulator <= phase_accumulator + 1220381325; end if; else phase_accumulator <= phase_accumulator + 1221381325; -- +/-1000000 end if; This is my email: rafael_u_r@hotmail.es my fpga is DE2-115 Cyclone IV and the audio codec is WM8731: Audio Codec, Signal name: AUD_ADCLRCK --Audio CODEC ADC LR Clock AUD_ADCDAT --Audio CODEC ADC Data AUD_DACLRCK --Audio CODEC DAC LR Clock AUD_DACDAT --Audio CODEC DAC Data AUD_XCK --Audio CODEC Chip Clock AUD_BCLK --Audio CODEC Bit-Stream Clock I2C_SCLK --I2CClock I2C_SDAT --I2CData My apologies if I ask too much, but it's a project, I'm doing at my university. I look forward to hearing from you soon. Yours sincerely Rafael Urquizo from Peru.
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  46. I had a look at this for SHA-1... Bitcoin uses SHA-256, so without looking in detail... * To work best you would like to generate one hash per cycle. * To work fast you need to unroll & pipeline any iterative process (aka rounds) and register the result of each round. * SHA-256 uses 64 rounds, each of 256 bits, so if you were to pipeline each at each round (to minimise levels of logic nd boost speed) you need 16,384 bits of state. * You will also need something to hold the current block (256 bits), and distribute bits to the rounds. This will need around around 256 shift registers, with an average length of around 32 bits = 8192 bits of state there. In summary, to process one 256 bit block of a SHA-256 every clock cycle, at the highest clock cycle, on a device with 8 flipflops per CLB would require a around 16386/8 = 2048 slices for the hashing, and another 8192/32 = 256 or so for distributing the data blocks to the rounds. = 2,304 CLBs. So an XC6SLX25, with 3,758 CLBs would be the smallest I expect you could squeeze a high performance implementation of SHA-256 into. Mike
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  49. Hi Steve, There is a lot you can do on the 250k for Audio projects, but as it only has a small amount of RAM the scope for DSP-style effects (reverb etc) are limited. Compared to a microcontroller (e.g. Arduio) it has a huge scope for weird and wacky sound synthesis - as projects like the Retrocade and the chip-tunes demonstrate. MIDI in/out is pretty simple (it's just a serial protocol after all...), Plenty of scope for things like an ultrasounic distance sensor to MIDI interface. One thing that Papilio can do that micro-controllers can't is generating high quality digital output. .(see http://hamsterworks.co.nz/mediawiki/index.php/SPDIF_out for an example). In-line audio processing is possible too - for example you could build an all-digital active speaker crossover to split out high and low frequencies. But a rule of thumb might be "Writing software is 10x quicker than designing equivalent hardware, so unless you want to chew through your time use a micro-controller (or an FPGA with a soft CPU like the ZPUnio or AVR8) if at all possible". As for wireless, it should be possible to use any wireless modules that works with Arduino - just do a quick search for "Arduino WIreless" on http://dx.com for examples. Of course you may need to port the driver across too!
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  50. I've just got DVI-D running on a Spartan 6, starting from scratch (well, the DDWG specs at http://www.ddwg.org/downloads.asp ) You can find the details of my project (incl all the vhdl source) here: http://hamsterworks....x.php/Dvid_test Feel free to use it in your own projects. Wonder if it will work on the Papilio Pro? Might have to butcher a cheap HDMI cable... Mike This post was covered on Hackaday too. http://hackaday.com/...m-vga-to-dvi-d/
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