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  2. Jack, found a few more broken links under Yes, there are tutorials there, but the image content is generally missing. Seems the links are broken in the densest, most useful tutorials. Making libraries, publishing tutorials, etc. Others seem to have images just fine, but they're the rudimentary ones. Here's an example. Every image url in this page goes nowhere; Also the link at the bottom; Here's the tutorial one, also missing images; Starting from the first library tutorial, standalone schematic, which has missing images, the links to the other library tutorials, SOC Wishbone Schematic and SOC Wishbone VHDL, are also dead. I sure hope those are around somewhere Cheers, Joe
  3. Seems like a good idea. Is there a way to do it? I.e. is there a way to either have a schematic component or an external pin drive the counter in the timer? Old VLSI timers like the M6840 have external clock and gate pins for the internal timers, and are also capable of generating interrupts. I've been thinking, if one could clock one of the timers externally, and preload the internal counter with, say "1", the thing would then count down once on an external signal event and interrupt the ZPUino! Instant external ZPUino interrupt hack! Two digital birds with one stone! Also, is there any ZPUino SOC example sketch which actually uses the timers, and timer interrupts? Cheers!
  4. Hello! Reading the documentation, there's a strong implication that there is some sort of default pin-mapping for GPIO pin operations (bare papilio pins) which is not specifically related to installed Wishbone peripherals. Where is it documented for each board? The ZPUino tech manual talks about redirecting input and output from slot peripherals to GPIO pins. That's fine, but then it talks about this: [4.1.4 Software GPIO pins should be manipulated using the Arduino-like functions digitalW rite(), digitalRead() and pinMode(). Additionaly GPIO can be bound to devices using PPS (Peripheral Pin Select). You can also use the following "C" macros if needed. Each pin block is 32-bit wide: GPIODATA(x) GPIODATA for pin block x GPIOTRIS(x) GPIOTRIS for pin block x] Short of writing a sketch which "pings" all of the Papilio's Arduino-style pins from inside a sketch (1-128?) and possibly crashing something, is there any way to do this on a default "naked" ZPUino? So, the real questions is, on a pro, one, duo, etc, running a ZPUino, when I set pin X to output and do a digitalWrite() to that pin, where does it come out, and how do I find that out? I know that I can tie a <wishbone to registers x 10> library symbol to my ZPUino in ISE, connect those registers to the outside, and maybe do my own WB_digitalWrite() function for it but making the very same physical Papilio pin both an input and an output using that part would need a tristate buffer or latch hung onto the side of it, and a way to control that in code the way Arduino GPIO does. EDIT: I also see a few examples that re-map the pins, i.e. the MegaWing_Logistart example, and the Flex_Pins example, but is there a default mapping if someone simply starts bit-bashing Arduino I/O lines? EDIT: Answered my own question...They're in the ZPUino header files \\hardware\zpuino\zpu20\cores\zpuino\board_<something>.h one for each product, for anyone looking for the definitions.
  5. sleat

    Interfacing with VHDL circuit with ZPUino

    Here's an example of one of the broken URLs you asked for, Jack. If you use the formula which normally works, moving learn into the domain name, and deleting it from the path, this one still gets a 404. What happened to this tutorial? As I recall, it was good! As I mentioned, I figured out how to do it in a basic ZPUino SOC sketch without any library, so converting it to a library would make for a nice example of something substantial connected to a sketch via wishbone, in addition to your existing examples. Cheers, Joe
  6. Thanks bnusbick and Jack! Yes, I ultimately found the new "learn" website, but the problem is that a number of the old URLs in the templates and examples need to be gone through and modified, as you say. The modification should be very formulaic, provided one knows where the goods are. It's really only a problem of context. I remember that the system even a short time ago was very good, you'd open a template, or a page on the site, and useful info would pretty much jump out at you. So, basically the flow of Open Template/Example/Default sketch=>Study Code/comments=>click to learn more=>Back to sketch and make broken, but not very badly. A search/refactoring tool with string handling would sort most of this out quick, when it sees the url form<something> it could simply convert to<something> and it should be fine. These may exist in many places in your web and IDE/Template content, for example "Learn" just above in the forum tabs is the wrong url. There are content links under "blog" that are also broken, so missing some pictures. Possibly related, in the IDE, when I click New DesignLab Library - Wishbone Schematic, it throws a java null pointer exception, so I've included the call stack below. Both other menu options, standalone and wishbone vhdl, work just fine! If this is only a local problem, can I safely re-install the IDE without breaking my existing xilinx ISE setup? The xilinx side seems to be working well so I don't want to mess with it. Now for the good news! I've come up with a library-free example which completely demonstrates hooking drawn schematics (in this case a 32 bit counter with select-able clock) up to Wishbone with just inline sketch-code. By polling the counter clock set to various speeds and displaying the value, one can determine the absolute limits of the ZPUino SOC in handling realtime synchronous stuff. (My synch-serial instrument spits 32 bit fixed-point at 1khz which I need to do math on in real-time) Ideally, I could figure out how to have the ZPUino do it on interrupts so as not to block, but I don't see an easy way to do that without an interrupt on wishbone input capability. Now if only I could clock the internal ZPUino timers with a GPIO pin...that'd fix it, since they can interrupt! As soon as I can figure out how to create a new schematic wishbone library template without the menu, I can make a library version too. Can anyone identify the background magic steps that this menu option does, <Papilio=>New DesignLab Library - Wishbone Scematic> so I can do it manually? I note that File=>Examples=>Template_DesignLab_Library_Wishbone_Schematic=>edit library exists, but doesn't really work as the menu options under Papilio do. It's also not the same as the standalone or VHDL examples next to it, since it has "edit library" as a button on the right. Do these examples have any purpose? I don't get a blank sketch with the instructions and a .cpp and .h template to work with. It's simply an example sketch with nothing "behind" it. For the one under "Examples" ending in "Wishbone_VHDL" Thanks again, I guess the most burning question is "Can I fix the java exception and make a wishbone schematic library without doing it manually (and possibly missing critical steps)?". New DesignLab Library - Wishbone Schematic_java exception.txt
  7. Yesterday
  8. Last week
  9. The content should still be there, we just need to fix broken links. Please let us know what you see wrong and we will work on getting things in order. should work for the learn content.
  10. Where did you find the preferences file? I have the same problem.
  11. I entered the following: and it took me there.
  12. Earlier
  13. Hi, Just getting the time to resume a 32 bit de-serializer circuit I want to make as a peripheral for the ZPUino to read a specialized instrument, and I've dead-ended trying to learn the stuff I need to build a complete project using DesignLab. I do remember making heavy use of articles under "Learn". Is there an alternative way to get to the tutorial content for building circuits, say from VHDL or schematic edits, and making them into parts that can be hung onto the wishbone bus? I'm also saddened to see that many of the formerly useful urls included in the DesignLab templates are also dead. Any alternative there? What happened to all that content? At least the YT videos are still up, but I'm having to watch each one to see whether it's helpful. Thanks in advance! Cheers, sleat
  14. Sounds good. Can you elaborate a bit more and explain how I would practically have to do it? I do have basic experience with docker etc. but I have no idea how to modify a container properly...
  15. Hello I have really weird login issues for days now. Basically I cannot login to this forum and my account. Whenever I logout I have to reset my password in order to be able to login again. I even tried copy-n-paste my password from a text-editor, does not work either. I have thus to assume that my password does not get stored properly, may be it's a coding issue - honestly I have no clue... I need help here!! Thanks and Greetings
  16. alex


    Hey guys, It's been a while since I was last here so I thought I'd pop in and say hi to all the old timers I used to know. I wonder how many of them are still here poking around, trying to beat them FPGA gates into submission A
  17. I tried to create a new account to shop on gadgetfactory but the recaptcha box at the bottom of the registering form says "reCAPTCHA V1 IS SHUTDOWN" and because of that I am not able to create a new account. All the best, kvintus
  18. I have a number of FPGA boards, including several Papilios, and recently acquired a Digilent Artix 7 CMOD A7. The nice thing about this board is the form factor (can plug into a breadboard), and the inclusion of a large SRAM (not SDRAM!). I found a number of projects on Hamsters web pages (excellent learning material BTW), specifically a project to use this board to output 1080p over a HDMI cable. I have spent the past few evenings converting the VHDL code into Verilog. It's not that difficult. I think that I have spotted a bug where the constant 720 is used instead of 1080 (the video is 1080p, but perhaps the code was original for 720p?). I have brought hsync and vsync out to pins in order to check timings on a scope (that's how I found the bug). I was puzzled as to why I was seeing no signals whatsoever on the high-speed TDMS differential pins, until I finally realised that they need 50ohm pull-ups to +3.3V. This is normally done at the other end of the HDMI cable, but I don't have one currently connected. I popped in some resistors and finally saw some waveforms on the differential pins. They were pretty nasty. I really need a scope with much higher bw! Just today I got a HDMI breakout board, ordered from Ebay. I will now be able to connect a HDMI cable to a monitor. To get started I really want to drop down the timings from 1080p to 576p (UK 50Hz standard definition), but I can't find the pixel numbers for the vsync, front/back porch etc. If anyone has a definitive list, please let me know! I can compile for either 1080p or 640x480 VGA timings (no idea if this will be recognised over HDMI). At 1080p I am failing timing analysis. This is where I struggle. I am using a PLL to boost the 12MHz xtal to the 100MHz needed by the original code. I am trying to define in the XDC the clocks. I know how to define the XTAL clock, but I am having problems telling Vivado about the internal clocks. In fact I am not sure whether I really need to or whether it can infer the clocks from the MCM parameters? I tried using the timinng constraints wizard, but it wanted to add constraints for the TMDS outputs, but I had no idea what numbers to use. Any guidance from anyone who has played with HDMI would be greatly appreciated. Once I have something (low res) working with the CMOD-A7 I will go back to the Papilio Pro and get something working here.
  19. With ISE it should be theoretically possible, because it is a X Windows application. So setting the DISPLAY env variable in Docker and enabling access to the X server from the container should make it working. I have not yet tried this on my own.
  20. I like the idea of having a VM to avoid all the install hassle. I finally setup a kubuntu 14.04 VM with DesignLab and ISE. I can offer that VM in case anyone wants it - however the license would have to be removed first. I ran your docker container as explained here and got cloud9 running. How can I run DesignLab and ISE? Is that possible?
  21. Wolfgang Egger

    Papilio LogicAnalyzer on Mac OSX?

    Hello, I have just bought a Papilio LogigAnalyzer Kit. On its page one can read the following: The software is an Open Source and cross platform Java client that works on Windows, Linux, and OSX. The client is integrated into our DesignLab software and if you use the FPGA for other tasks it just takes two clicks to get back to Logic Analzyer functionality. The Logic Analyzer is always just two clicks away! Until now I have not found this software for Mac OSX. Could you please provide me some information or a link to the download-area of this software. Have a nice day
  22. Jaxartes

    What is a good source of reset signal?

    Not if you pass the result of all your reset logic through a register before using it as a reset -- which I recommended above (in my 2nd post) for other reasons. Then it shouldn't make any difference, to that warning, what is controlling the register. I think the cause of the warning is not with using the pin for something related to reset, but only with directly driving reset from it. The Xilinx tools will try to figure out how long signals take to propagate from where they originate to wherever they are needed. There can be a problem if they take too long, or if the time is too hard to predict. The register improves both. I don't see anything in the warning about fanout, either. I've read about reset fanout being a problem, but haven't encountered it. But then, my designs have been fairly small, have not demanded the utmost of performance, and have used synchronous rather than asynchronous reset.
  23. Cactus

    What is a good source of reset signal?

    Thank you! I have now done just that, and it works. Wrapping the whole design into a toplevel VHDL module is a bit of a bummer (since I now have to manually "forward" all real IO from the real Clash code to the IO of this wrapper), but I think there should be a way around that by somehow getting Clash to automagically instantiate a VHDL part and thereby avoid this inversion of structure. Wouldn't that still have that problem of too much fanout, like in the original Xilinx warning?
  24. martinayotte

    JTAG JP4

    I've read this topic : Unfortunately, this is NOT true ! Even if JP4 jumper is installed, either the papilio-prog or sc3sprog tools will report the presence of the LX9, this means the JTAG TDO line of LX9 is not in tri-state and will respond to any JTAG commands. The JTAG header is in parallel with the LX9, so any external JTAG devices will have their TDO in parallel with LX9 producing garbage communication returned to FT2232 input, which is exactly what papilio-prog or sc3sprog tools are showing : mixtures of collisions of bits returned by 2 devices fighting each others. The workaround would be to have both LX9 and external devices placed in JTAG daisy chain like most design provide, having each devices TDI attached to previous TDO and the last TDO returned to the FT2232, but it is not how the PapilioPro is routed ... So, conclusion, PapilioPro JTAG header is completely useless for programming external devices ...
  25. Jaxartes

    What is a good source of reset signal?

    Additional tip: The output of the reset logic should be synchronized by a register. That's to avoid glitches which might be troublesome with an async reset.
  26. Jaxartes

    What is a good source of reset signal?

    Can you insert a small amount of VHDL (or Verilog) code into your Clash design, and use its output as a RESET, instead of taking RESET from an external pin? Using initializers it'd fairly easy to generate a 1 for a few clock cycles after the FPGA is initialized, and 0 afterwards. It can also be combined with a button so you'd have both ways of causing a reset. It seems like something that would have already been done, and made available as a Clash primitive, by somebody. As I think about it, you might be able to do it just in Clash, with two resets: the "outer reset" is either always 0, or is driven by a button, and is only used by the reset logic the "reset logic" has a few bits of state that's initially zero, and filled in with ones the "inner reset" is driven by the reset logic, and is the NAND of the reset logic's state Not sure of all the details, as I've never used Clash.
  27. I'd like to use CLaSH ( with a Papilio Pro. By and large, it works; however, CLaSH requires an asynchronous, active-high reset spike to initialize registers. This is because CLaSH generates assignments on RESET only, instead of initializers; here's an example VHDL generated from CLaSH: -- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.blinkertop_types.all; entity blinkerTop is port(-- clock CLK_32MHZ : in std_logic; -- asynchronous reset: active high RESET : in std_logic; LED : out std_logic); end; architecture structural of blinkerTop is signal \#tup_app_arg\ : unsigned(31 downto 0); signal \s'\ : boolean; signal \#s'_case_alt\ : boolean; signal s : boolean; signal \#finished_case_alt\ : boolean; signal \#k'_case_alt\ : unsigned(31 downto 0); signal ds : blinkertop_types.tup2; signal \#finished_app_arg\ : signed(63 downto 0); signal x : unsigned(63 downto 0); signal x_0 : blinkertop_types.tup2; signal \x#\ : unsigned(63 downto 0); signal k : unsigned(31 downto 0); signal \#w\ : unsigned(63 downto 0); begin LED <= '1' when \s'\ else '0'; \#tup_app_arg\ <= resize(to_unsigned(0,64),32) when \#finished_case_alt\ else \#k'_case_alt\; \s'\ <= \#s'_case_alt\ when \#finished_case_alt\ else s; \#s'_case_alt\ <= false when s else true; s <= ds.tup2_sel0; \#finished_case_alt\ <= tagToEnum(\#finished_app_arg\); \#w\ <= (\x#\ + to_unsigned(1,64)); \#k'_case_alt\ <= resize((resize(\#w\(31 downto 0),64)),32); -- register begin blinkertop_register : process(CLK_32MHZ,RESET) begin if RESET = '1' then ds <= ( tup2_sel0 => false, tup2_sel1 => resize(to_unsigned(0,64),32) ) -- pragma translate_off after 1 ps -- pragma translate_on ; elsif rising_edge(CLK_32MHZ) then ds <= x_0 -- pragma translate_off after 1 ps -- pragma translate_on ; end if; end process; -- register end \#finished_app_arg\ <= to_signed(1,64) when x = to_unsigned(32000000,64) else to_signed(0,64); x <= resize(\#k'_case_alt\,64); x_0 <= ( tup2_sel0 => \s'\ , tup2_sel1 => \#tup_app_arg\ ); \x#\ <= resize(k,64); k <= ds.tup2_sel1; end; (Note how `ds` is not initialized but set in the `blinkertop_register` process when RESET is high) Of course, for a simple circuilt like above, where the initialization is for 0 anyway, just setting RESET to always low works; however, any slightly more complicated circuit will need register initialization to non-0 values as well. In these cases, I really need the spike. Is there a pin on the Papilio Pro that I could use in my UCF file to get this reset spike? I was able to get it working, in more complicated circuits requiring non-0 initialization, by using a (negated) LogicStart joystick direction, but this approach has two problems: I am getting a warning from the Xilinx tools that the joystick input shouldn't be used for reset or anything clock-like: WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <RESET> is placed at site <P57>. The corresponding BUFG component <RESET_IBUF_BUFG> is placed at site <BUFGMUX_X3Y13>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <RESET.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. I would like my circuit to start in an initialized state instead of requiring me to press a button
  28. Jaxartes

    Where can I buy Papilio Plus or similar?

    Papilio DUO from Gadget Factory has SRAM (512kB or 2MB). Pepino from has SRAM (1MB). The FPGA chip in both is the same.
  29. Hi guys, I want to learn to create SRAM controllers and I've seen this Papilio Plus board is perfect because it has a SRAM module, but I think it's discontinued. Papilio PLUS: Do you know where can I buy this board or any other one (Xilinx) with a SRAM module? Thank you very much.
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