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  3. How do you invoke ise in windows 10 from the edit circuit button in DesignLab now that ise runs virtually under VirtualBox ? Regards Tony Smith
  4. FuseSOC for managing Papilio projects and libraries.

    Hi Olof, thanks for passing by. First I must say, that I'm only a happy GadgetFactory customer and Papilio Pro User. The big advantage of the Papilio Pro is that its SDRAM can be accessed with an open source soft core without having to rely on proprietary IP of the FPGA vendor. FuseSoC is a in addition a genius idea to solve the problem of having a tool vendor independent build description. I heard about LibreCores, FuseSoC and FOSSI at the FOSSIC RISC-V event last year in Munich. The funny thing is, that I didn't gave FuseSoC much attention until Jack started to play around with it after my hint. After his initial proof of concept I realized how easy to use FuseSoC is. In the meantime I updated Bonfire a lot, separated it into several FuseSoC cores, and also created a few Dockerfiles which allow to create a complete Build environment for Bonfire, including the RISC-V toolchain, ghdl for simulation and the tools to build eLua for Bonfire. Of course I have the same problem as you, lacking time, especially for Documentation. I have also a version of Bonfire / eLua running on a Digilent ARTY board including TCP/IP networking. Because its uses a Xilinx IP Integrator block Design (for accessing SDRAM and Ethenernet PHY with Xilinx IP) it cannot be build with FuseSoC yet. Maybe the tcl Script option you mentioned above will help to solve this. I already considered it. Also here the limiting part is that the cores are not fulfilling my own standards regarding documentation yet... Many thanks, I'm thinking about it. But as stated above I'm just a Papilio Customer Regards Thomas
  5. Last week
  6. I want to use uncompressed .wav files to add sounds to my game. There aren't any audio examples in Designlab besides the Modplayer, SID, and YM2149. All of which sound like they are hard to convert .wav format to. I'm using the Modplayer now, but want to use the .wav sounds I have. What is the best and/or easiest way to achieve this hardware wise?? I'll load the wavfiles from my microSD-wing like the .mod files. It's a retro-style game so high-quality sound isnt important. I'm thinking uncompressed 8-bit, 8khz .wav audio would be ok, then I wouldnt need a codec, and probably easier to clock than 44.1khz or 22.050khz. Can I use the Audio Passthrough to the AUDIO_zpuino_sa_audiomixer and reclock it, or use delta-sigma dac and reclock? Any advise would be greatly appreciated! Thanks
  7. Hi Jack and Thomas, I just stumbled across this discussion in my semi-regular googling to see if FuseSoC has picked up any new users. Exciting read. I really like the Papilio ecosystem and have been planning on buying some boards. Unfortunately, I have realized that it's lack of time rather than lack of HW that prevents me from playing more with FPGAs outside of work. Anyway, I'm happy to help out and answer questions. I know that you have both contributed patches to FuseSoC already. Also, let me take the opportunity to once again apologize for the embarrassing lack of documentation. I can however answer one of your earliest questions right away. If you create a file in a fileset with the tclSource file type, it will be picked up by ISE and sourced in the main TCL script that creates the project file. As other backends also support sourcing TCL files, you should add a usage = ise to make sure it's not picked up by other tools. Regarding the inelegance of having .core files with or without provider sections, depending on if their local in the source tree or external... I'm aware of that. I have some ideas for how to make that slightly nicer, but it's not prioritized right now. I will get back once I have more to say about that I was wondering a bit about this one. Couldn't really figure out what you mean. Could you elaborate a bit and perhaps I can see if this is something that is already handled or that I could add handling for. Anyway, hope to find time to try out the stuff you have packaged. Already built and tested bonfire-soc, but not the zpuino stuff. Also, make sure to register your projects at librecores.org. We are building an index there of interesting open source silicon projects. The registration process is very streamlined and should only take a moment. Right now it's mostly an index, but we plan to expand this to automatically handle CI and show relations between cores (especially for FuseSoC-compatible cores) in the future. Consider this also an invitation to our yearly conference, ORConf. We would love to see some presence from the Papilio corner and I believe many in our audience would like to hear a presentation of your work Cheers, Olof
  8. Earlier
  9. data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  10. data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/tx_unit.vhd#L54 or https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/spi.vhd#L45 and https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/sid_filters.vhd#L22 It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?
  11. How do I convert a Pro project to DUO?

    Hello Robin, We would need more of the error message that you are seeing. You might need to scroll up and look through the log files until you see what is going wrong. You can also attach you project here and I can take a look at it. Jack.
  12. WARNING: Newbie here! I'm trying to run this Pro project (gadgetfactory.net/learn/2015/05/03/designlab-make-a-simple-fpga-circuit-2/) on a DUO. I've changed the I/O markers to use ARDUINO_0 and ARDUINO_1. Probably not the best choice but I'm just trying something past the 'Generate Programming File' stage. No matter what I try the result is always 'Process "Synthesize - XST" failed'. Any idea? If more information is needed, just ask Thanks Robin
  13. Where can I download the design source files (PIC, FPGA, PCB schematic/layout) for the OpenBench Logic Sniffer v1.04 with the latest Demon core and PIC code? I have seen answers in the other similar posts here (http://forum.gadgetfactory.net/topic/2482-hardware-source-files-for-openbench-logic-sniffer/, http://forum.gadgetfactory.net/topic/2812-gadgetforge-is-down-is-there-an-alternate-url-for-the-files/), but only the PIC and FPGA hex/bit files are present (no source code) at the specified locations, and gadgetforge links are dead. Nor are any hardware design files present there. Thank you.
  14. How does data get from the PC to the Spartan-6 Flash

    Xilinx call it indirect programming. See https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pim_c_introduction_indirect_programming.htm The second serial port is available as a regular serial port (virtual COM port) to the user for any purpose. It's commonly used with a soft CPU to implement an embedded system. Magnus
  15. How does data get from the PC to the Spartan-6 Flash

    @Magnus, as always thanks for taking the time to respond. Couple of further questions follow on, I'll apologise in advance, I am quite new to this 1) Is there an app note available on this technique? I can imagine its not a 'unique' application. 2) What's the purpose of the second serial interface from the FTDI device to the FPGA (MPSSE)? many thanks Andrew
  16. How does data get from the PC to the Spartan-6 Flash

    Almost got it right First a a flash programming bitfile is sent to the FPGA via JTAG. This bitfile uses a special library component (BSCAN_SPARTAN6) that allows the logic fabric to access the JTAG port. Flash SPI programming commands are then sent to the FPGA via JTAG, which will forward them to the flash chip. Magnus
  17. How does data get from the PC to the Spartan-6 Flash

    @johnbeetem Thanks for that....now I can see what is being done. My mistake, I thought all bitstreams where automatically loaded to the FLASH from the PC software, but, what you've pointed out makes perfect sense now. In normal use, the FTDI device becomes a JTAG programmer sending the configuration directly to the FPGA. Then, if you want to program the FLASH so the board can be stand-alone, there must be an option in the software that firstly JTAGs the FPGA to be the FLASH programmer, using the second serial bus generated by the FTDI device as the data stream... thanks again Andrew
  18. SDRAM controller for Papilio Pro

    OK, the problem was in my SPI driver. I changed MISO on the falling edge instead of rising edge. Now it seems like issue is solved.
  19. How does data get from the PC to the Spartan-6 Flash

    I've never programmed the Flash: I always use Papilio DUO connected to a PC. So when I power on my DUO it loads the original bitstream from Flash and the LED blinks, along with all the other pins. Once the initial configuration is loaded, I can overwrite it from the PC by downloading a bitstream over the Xilinx JTAG pins, which are connected to port 0 of the FTDI chip. JTAG is always available no matter which other configuration mode is selected by M0/M1. I don't know how to reprogram the Flash. I think Gadget Factory has a bitstream you can download using JTAG which temporarily turns the FPGA into a Flash programmer. Hope this helps!
  20. Hello Forum, My first time on a Forum, hope I get the etiquette correct. Recently got my Papilio Duo and a LogicStart wingy, itching to get it all running. Intend to VHDL, not drag and drop...that's the intention anyway. Essentially, being from an electronics background, I like to know what's going on. To that end, I've been wading my way through the plethora of Xilinx datasheets associated with the Spartan-6-LX9. At the moment I have couple of quick questions for the collective forumers The LX9 FPGA is set with M0 =1 and M1 =0, this sets the device in Serial Master Mode so it will get its configuration bit stream from the Flash on power up or if PROGRAM_B is pulled low, so : 1) How does data from the PC get programmed to the Flash? 2) I see other questions relating to the PC software configuring the FPGA directly through the USB port,, am I missing something in the circuit diagram, I cant see how this is possible? Unless there is something pre-configured, pre-programmed that we are shielded from....... hope they're not too stupid questions. Thanks Andrew
  21. SDRAM controller for Papilio Pro

    OK, seems like I've figured out the root of the issue. This is the SPI signal from MCU when FPGA is powered off And this is what I have when I power FPGA on This is zoomed image What can cause those pulses? The constraints file is included Kind regards, Sergey constraints.ucf
  22. I'v made a custom papilio pro board based on schematic and eagle pcb file that published, the board has 16mb flash spi instead of 64, I loaded the quick start bit file to the board and everything just go fine.both to SPI or FPGA. the problem is when I tried to open the port of the FT2232 chip with putty as a serial monitor program, nothing show up, I pressed buttons on keyboard and just some character show, and the rest are garbage( if I flashed to FPGA), and putty go freeze if the bit file loaded to SPI (blank screen) I use 32mhz OSC, voltage regulator just fine as I checked, What more I need to check to solve this problem? thanks all sorry for my bad English
  23. SDRAM controller for Papilio Pro

    I've made the changes you mentioned regarding the simulation. Now it looks like this wbs_dat_o is still undefined by this moment, thus it remains 'U'. And this hasn't solved the hardware issue...
  24. SDRAM controller for Papilio Pro

    Printing cartridge, inkjet one
  25. SDRAM controller for Papilio Pro

    What do you mean with "cartridge"?
  26. SDRAM controller for Papilio Pro

    Hi Sergey, your wavewforms look a bit strange... First I see some "undefined" values (where the waveform is in the middle between 0 and 1). In a real circuit there are no "undefined" values, in an FPGA it will be either 0 or 1. When your code has something like if signal='0' then ... endif it will never execute the then part in a simulation when signal is e.g. 'X' or 'U' , but in a real circuit it will most likely fulfill the condition. So you should clean you design in the simulation that it does not contain undefined values expect in areas where you really expect it (e.g. on reset...). Than I'm wondering about your wishbone ack signal. I assume that every 1 pulse of the spi_data_ready is a new data word. Then I would expect one Wishbone write transaction with exactly one ack pulse. Put you have a lot of them without any change in data and address. So you write the same word a lot of times. This itself will not directly doing any harm, but it gives me a hint that your design is not working as intended. Maybe you should take a look into the Wishbone B4 spec (just google it please...) Thomas
  27. SDRAM controller for Papilio Pro

    Also I've noticed a weird thing. Some background first. The device I design is the cartridge driver which should receive data via SPI from the MCU and then read and send to cartridge. So the weird thing is when I add the delay between data I send to the cartridge to see in the display what actually I received, it works good all the time. I receive the correct amount of data and the data itself is correct. But when I remove this delay to print data with the high speed the problem returns. I don't know how this part can influent on data read from SPI. There is an independent process which controls the cartridge, and it starts only on demand and after the SPI transaction is finished. Maybe there is some internal interference in the FPGA structure, I have no idea...
  28. SDRAM controller for Papilio Pro

    Hello Thomas, I'm not sure if I allowed to send the whole design due to NDA. Though I can share required information. The SPI data rate is 500 kHz to 10 MHz (I tested in this range, and result is the same). SDRAM works with 100 MHz clock frequency. The amount of data is tens - thousands of kbits. The start of the SPI transaction is showed in the simulation below. You can see both SPI data and Wishbone data in it. And here's the finish of the SPI transaction Here I send 220 x 32 = 7040 bits. The simulation code is cs <= '0'; ------------------------------- for i in 0 to 219 loop temp <= std_logic_vector(to_unsigned(i, temp'length)); for j in 0 to 31 loop sck <= '1'; if j = 0 then mosi <= '0'; else mosi <= temp(31); end if; wait for 10 ns; temp <= temp(30 downto 0) & '0'; sck <= '0'; wait for 10 ns; end loop; end loop; wait for 10 ns; cs <= '1'; I don't know if this information is useful though... Kind regards, Sergey
  29. SDRAM controller for Papilio Pro

    Hi Sergey, it will be hard to help you without having a look in your whole design. I'm missing also a lot of information about e.g. the data rate, the clock frequencies, the amount of data. It would also help to post e.g. simulation waveforms of the SPI and Wishbone interfaces. As an general advice I suggest you to strip down your design to the key building blocks and test them separately. You can also do this on the hardware. When you start with a design using block RAMs you can avoid a lot of pitfalls. BRAMs are dual ported so you can easily use read and write processes without taking care of data contention. The LX9 has 64KByte of BRAMs so it should be enough for some basic testing. Regarding simulation you should build unit tests for the parts of your design and check how they work. Maybe you can look at https://github.com/bonfireprocessor/bonfire-dcache/blob/master/tb_dcache.vhd as an example. It contains also test code to "consume" data from a wishbone master (process mem_simul). Thomas
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