All Activity

This stream auto-updates   

  1. Past hour
  2. The Papilio DUO uses the FT2232H, which is great (high-speed USB, 480 Mb/s). The Pro uses the FT2232D (full-speed USB, 12 Mb/s). I don't have a Pro so I have no personal experience. I get 200 ms or so for the Papilio One 250K, which is within human reaction time. The 500K is more like 500 msec, which adds significant delay to compiling and loading a small design. This is with my Flavia software, so the compile step is less than a second for a small design.
  3. Hmmm... the old Papilios use the FT2232D USB chip, the newer ones (e.g. Papilio Pro) the FT2232H high speed variant. With a more recent board, uploads "should" be fast. I'm using high speed (30 MHz, clock divider 0) JTAG with the -H chip routinely. For xc3sprog, it may be enough to write cables.txt via command line option, then edit the clock rate. I think I've done that once and got upload times (but probably for a compressed bitstream) 200 ms or so.
  4. Today
  5. Is the Papilio 250K coming back some day? For a long time I've recommended it as the best value for getting started with FPGAs and I'd like to know if I should still be doing so. I was playing with mine today and I love it way it downloads so quickly.
  6. Yesterday
  7. Here are some tutorials about arduino use, you can go and see! This is what big question.
  8. Yay, glad you got it working. If you want to trade it out for a new one just send us an email at and include a link to this forum thread. Thanks, Jack.
  9. Last week
  10. Hi, you could check Trenz TE0725 with Artix 7 up to -100 size. I once had a Microblaze on one of them (was replaced later in the design cycle) and it definitely utilized less than 1/3 of resources. You'll want the Digilent-licensed "XMOD-FTDI" adapter to use the debugger (no idea how hard it is to set up with multiple targets, there is one JTAG option USER1-4 in the MB config that might be relevant). There is a 1.8 V variant, most likely 3.3 V is the better choice. To put it into perspective, it's probably 2x...3x the price of a Papilio. With Vivado on Artix I think you have more microblaze configuration options than on Spartan with ISE. Note: I'm not aware of any ready-made solution to access the memory module on that board. For the Papilios there are soft memory controllers, and Pipistrelly can use the hardware core that's bonded out on the larger FPGA sizes. And, for Spartan 6 there is some community but I haven't found that yet for Artix...
  11. thanks will see if i can get @vlait or @Jack Gassett to regenerate the base hardware with those changes and will modify RV to use the new file, and maybe make a base hardware file for superglob that has all 3 buttons mapped somewhere, as i dont have the ISE installed anymore do me a favor and don't distribute the romgen version without linking back and a note that its "as is" meaning i am not maintaining that fork as it does exactly what i needed it to. i sent the changes to the original author but he didn't see fit to add them into his main branch. i am glad you got it working. it was driving me crazy.
  12. At last i will make it work. First you need to uncompres the mame set or jumpshotp and extract in in ./roms/jumpshot or roms/jumpshotp directory Then execute the ./scripts/build_roms_jumpshot.bat or build_roms_jumpshotp.bat and créate the files in the ./build dir. Then edit the pacman_video.vhd and go to line 316 and comment the clk and ena lines (This modification fixes the gliches of super blob too, remaking the PROM4_DST.VHD and PROM7_DST.VHD with the "c" token instead the "r l e" one...) col_rom_4a : entity work.PROM4_DST port map ( --CLK => CLK, --ENA => ENA_6, ADDR => col_rom_addr, DATA => lut_4a ); make the same in the 424 line col_rom_7f : entity work.PROM7_DST port map ( --CLK => CLK, --ENA => ENA_6, ADDR => final_col, DATA => lut_7f ); edit pacman.vhd and go to he end to set the controls you like. p_input_registers : process begin wait until rising_edge(clk); if (ena_6 = '1') then -- on is low in0_reg(7) <= '1'; -- ? in0_reg(6) <= '1'; -- coin2 in0_reg(5) <= button_debounced(8); -- coin1 in0_reg(4) <= '1'; -- ?Reset in0_reg(3) <= button_debounced(1); -- p1 down in0_reg(2) <= button_debounced(3); -- p1 right in0_reg(1) <= button_debounced(2); -- p1 left in0_reg(0) <= button_debounced(0); -- p1 up in1_reg(7) <= '1'; -- ? Table 1=Up / 0=Coskctail in1_reg(6) <= button_debounced(7) and button_debounced(13); -- start2 y fire p2 in1_reg(5) <= button_debounced(6) and button_debounced(4); -- start1 y fire p1 in1_reg(4) <= '1'; -- Board Test in1_reg(3) <= button_debounced(10); -- p2 down in1_reg(2) <= button_debounced(12); -- p2 right in1_reg(1) <= button_debounced(11); -- p2 left in1_reg(0) <= button_debounced(9); -- p2 up -- on is 1 freeze <= '0'; dipsw_reg(7) <= '1'; -- ? dipsw_reg(6) <= '1'; -- ? dipsw_reg(5) <= '0'; -- 1 Credit 1 Play (0) dipsw_reg(4) <= '1'; -- Free Play (0) dipsw_reg(3) <= '1'; -- ? dipsw_reg(2) <= '1'; -- VGA hz? con 0 la VGA se ve mal. dipsw_reg(1 downto 0) <= "11"; -- Play Duration 01=2:30 11=2:00 / 10=1:30 / 00=1:00 end if; end process; Resintetize.... and play. If someone need help i will make my best. I dont have a papillo but have the same fpga. jumpshot.7z
  13. Nice that you got it working. Just make sure no one reads this as a recommended first-step response to a board that doesn't show on USB... My experience: I've thrown some of my own (boxed) FPGA designs across the lab and smashed them against hard surfaces under the pretense :-) of drop testing. Several dozens of units. While this led to mechanical design changes, I've never managed to break a crystal, or in fact anything electronic on a board. So I wouldn't be too worried about shock-sensitive crystals. To me, this seems a failure mode as likely as thousands of others.
  14. i used my romvault papilio edition to do it. but it wont work on base pacman driver because either the address lines or the data lines are swapped in the jumpshot cpu. easiest way is to get RV Papilio Edition and modify the xml file hashes for the roms for jumpshot and replace your hardware file (or add a new type) in the same xml file OR try to figure out how my pscript (between the <papilio> tags works from the xml file and run the command line manually the version on the gadgetfactory download and gadgetfactory github site of romvault-papilio edition still uses a separate romgen (modified) which is able to read the ini files from the patches/Arcade/ directory so you can go that route no time to dig into it further at the moment, but if you cant figure it out, let me know and i see what i can do.
  15. What is the script to make the jumpshot roms? I cant make that game start with the pacmam driver.... I fixed some games gliches removing the clk and ena signals in the prom roms... If you say me how to run junpshot in the pacman driver i can try to fix gliches too.
  16. Earlier
  17. If got to same trouble in Windows (usually nothing happens when you try to run papilio-loader) go to c:\Users\..user_name..\AppData\Roaming\ and delete papilio-loader content preference file. Don't forget to end Java bin processes in Task Manager before running papilio-loader again.
  18. Help yourself! You may see my brand new Papilio DUO working with my brand new Crystal! Keep in mind that Crystals are shock sensitive and can be damaged during transport. In general - no sense to send forth and back the board for a quarter cost part as long as you know what you doing.
  19. Connecting the mini-USB cable to a comp. my Papilio DUO board powers up (Power LED lits up and a green 'LED' blinks), but no USB device appears in my Device Manager nor try even to connect a new one. I checked several cables (one I use in my LPC-Link IDE successfully) and several computers with Windows 7, 8, 10. When I switch to micro-USB, I get a port for AVR. Papilio-loader reports: 'Could not access USB device 0403:6010'. Of course . I see a couple of similar publications in Forum but a total miss of reaction to plugging USB cable didn't match. I will appreciate any help. P.S. 12MHz osc. of FTDI does not work. pin 36 SUSPEND# = 3,3V (active low when USB is in suspend mode) pin 60 PWREN# = 2,5V ( =1 USB SUSPEND mode or device has not been configured)
  20. I fixed paths (not yet on master) and generated a ZIP export file. Should work... not sure - fails on my side with: INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at Care to try ? Your luck may vary... Alvie
  21. I need to update that project file... I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around. Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though). Alvie
  22. You need to use make to synthesize the project.
  23. Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly. Alvie
  24. It is a Xilinx project?
  25. Oh thank you, I will try to recompile. I've also recompiled the bscan spi file with my constraints. I have an error trying to program the spi even with papilio prog and xc3sprog (with the fixed bscan)... I dont know why...
  26. Hello, It's black boxed because it greatly speeds up the synthesis time for the end user and most people have no need to modify ZPUino, just the peripherals attached to it. The source code for the black box is here: Jack.
  27. Sorry, that site has been offline for quite some time now. Jack.
  28. Thank for than change. I was looking for something like that. But i see that the first zip is corrupt. Can you repost it wiith the memory core for a standard xlinx? Im new in this of fpga... Thanx in advance.
  29. I'm trying to recompile adding some files to the project because lost links and now the error is caused by ZPUino_Papilio_One_V2_blackbox.ngc, cause ISE says it is for Spartan3 VQ100 only. What is this core and why it is blackboxed?
  30. Oh I just realized the papilio one have XC3S250E-VQ100 and my board XC3S250E-4TQG144C... But I think I've seen some TQG144G.. maybe I'm confusing myself with papilio pro. Anyway.. ¿how to change the configuration file into the designlab? Edit: I've found: DesignLab-1.0.8\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_One_250K\papilio_one.ucf If I modify only this file it will be ok? (I dont know how designlab call ISE and if there is snother configuration file...) Thanks
  31. Load more activity