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  3. Jack, I should have sent you this file instead of Papilio_DUO_LX9save5_works.sch as an example where the clocks work. Regards, Blake Papilio_DUO_LX9_works.sch
  4. Last week
  5. Hi Jack, I have been trying out the steps you suggested, and I got them all to work. Thanks for the suggestions. Besides the original question of how to write to a wishbone register in VHDL, I have the remaining questions from my previous emails. 1) I could get clock input to the counter circuits by connecting clk_osc_32MHz to clk_32MHz (see the attached Papilio_DUO_LX9save5.sch). However, if I just created an IOB of clk_osc_32_MHz and connected it to clk_32_MHz, the wishbone register reads always read 0. Shouldn't these be equivalent? Also, when I tried to connect on IOB of clk to clk_32_MHz, it got the following error when I tried to generate the bit file (see the attached Papilio_DUO_LX9.sch). ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. (I got the same error whether I made clk an input or output.) 2) What does connecting a wishbone register's input to its output do? When I don't connect the wishbone's register to its output, I still see the counter output that is connected to the wishbone register input when I read the wishbone register output. I also encountered the following annoyances. Whenever I opened ISE using edit circuit from DesignLab, ISE hung when I saved the .sch file after making changes. It did save the file though, so I could just end the ISE process and edit the circuit again to see my changes. To get around this annoyance, I would run ISE outside of Designlab, and just use Designlab to load the circuit. I also had to change the name of the generated bit file from Papilio_DUO_LX9.bit to papilio_duo_lx9.bit, since Designlab load circuit would only recognize it if it was in all lowercase. Regards, Blake Papilio_DUO_LX9save5_works.sch bfn_counter.vhd Papilio_DUO_LX9.sch
  6. Hi Jack, Thank you for the response. I've tried both the 'Audio_RetroCade_Synth' circuit and sketch from DesignLab 1.0.8 (loaded circuit first via lowest numbered com port for the Papilio Pro, then sketch uploaded via the higher numbered port) and also the: RetroCade-1.3-lcd-contrast-fix-zpuino-2.0-PapilioPro-S6LX9-RetroCade-1.3.bit bitfile which is the latest one I could find and seems to be the same one you linked to above. Those are the ones I tried from the first time I unpackaged the RetroCade and both behave the same way with the issues listed. I did try the 1.1 bitfile just for the heck of it and that was a no-go for sure. Any other ideas on how I might troubleshoot this? It is a bit perplexing to see the the erroneous midi commands show when looking at the debug via the RetroCade, but not seeing them when watching the midi traffic from the midi controller itself and also not seeing the issue at all when using the PC keyboard via a com port connection to the RetroCade Synth Dashboard. Unfortunately I currently don't have access to another midi Keyboard to test with. Thank you, Anthony
  7. Or try this bit file: 1.3.1 should be latest version with LCD fix. Jack.
  8. Hello Anthony, What version of the RetroCade code are you running? I think if you try the very latest version by downloading the DesignLab software and using that to upload the latest code you might see the problems go away. Jack.
  9. Hello Blake, Sorry for the slow response, I've been on a job which was running late every night last week and then Fathers day weekend this weekend... I should get some time this wednesday to take a look at this and help out. Jack.
  10. Jack, When I try to add clk to the attached schematic, it complains with the following: Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. I don't see clk listed in the .pcf file that contains the net list, but somehow it knows that it is P94. I do see the following in the .pcf file: COMP "ext_pins_in<0>" LOCATE = SITE "P94" LEVEL 1; but when I tried to name the i/o connector ext_pins_in(0), it didn't like that either. So, what do I need to do to make the attached schematic output a 30 Hz signal on I/O pin Arduino8? Regards, Blake Papilio_DUO_LX9.sch
  11. Hi Jack, Could you provide a link to the example of creating a counter in the schematic editor? I don't see it on your learn site. Regards, Blake
  12. Jack, I don't understand what connecting the wishbone reg0 inputs to the wishbone reg 0 outputs does. Even when I disconnect reg 0 input from reg 0 output and apply vcc to one of the bits of the reg 0 input, I see it on that bit on the reg 0 output, so they still must be connected in some way. Could you explain the difference between the two scenarios? Regards, Blake
  13. Update: Even though I'm having no issues with the midi controller I'm using with other midi hardware/apps I decided to use a midi monitoring app to watch the messages being sent from the controller to rule out any issue with it. When the 'random note' or note off issue occurs on the RetroCade I see no data being sent from the controller that would cause it within the monitoring application. This controller is of the type that sends continuous 'Active Sense' messages, but I don't see how those would cause this issue with the RetroCade.
  14. Earlier
  15. I just recently started testing my new RetroCade synth along with a Papilio Pro and, aside from the LCD on my RetroCade having issues (not all of the characters on the bottom row display properly and only a vertical line moves across the top row rather than a 'space invader'. Pressing on the black frame on the edge of the display while using male/female jumpers to connect it to the Retrocade fixes this so it seems it's just a bad connection on the LCD itself and not on the RetroCade PCB so I can probably find a way to fix that myself.) and it was also missing the small black cover for the five-way switch (I left a message via my GadgetFactory account regarding the button, but I think there may be an issue there since I didn't get a response so I just ordered a few spare button covers to have). Those are fairly minor things, but I'm also having the issues that were described in the post linked below: http://forum.gadgetfactory.net/index.php?/topic/2713-problem-with-the-channels/ All 8 Channels are called "SIDV1". Shouldn't there be at least one YM2149 channel? Channel 0 Drums don't produce any sound Channel 1 seems to be the same as Channel 0 Channels 2 - 7 are playing the last key pressed constantly, I can only stop when turning off the power When I press keys on my Midi Keyboard in Channel 0 too fast one these things will happen: a broken bass noise appears note off doesn't work until I press another key random notes are being played I followed-up on that post by checking the chat session on gitter that was linked to in the post, but I didn't see anything about #4 and 5 in the chat log. I'm using an old Kaysound MK-4902 midi controller that I've been using for ages and I have no issues with that controller and my other midi applications so I'm guessing there is something between it and the RetroCade that isn't quite right. I was thinking I just got a faulty RetroCade unit due to the odd issues aside from the ones above I was seeing such as the LCD not working correctly, stopping, starting or changing examples files from SID, YMD, etc... on the smallFS via the onboard five-way switch will often cause the RetroCade to either lock-up, start playing white-noise, random clicks/tones, or sometimes all of those odd things at once and I have to power it off/on to get it going again. Using the RetroCade Synth Dashboard and the computer keyboard while connected via the com port doesn't seem to produce issues #4 or 5 above and switching between the three available MOD and YMD loops via the deshboard doesn't freak it out like it does when using the onboard joystick. I've tried different USB power supplies with known good +5V and plenty of mA and the issue presents regardless of that so I don't think it is a power issue when using the MK-4902 external controller. I've also used a midiplus USB 2-channel controller through my PC rather than MK-4902 directly to the RetroCade and that made no difference. I'm using v1.3 of the bitfile. When I load the .ino RetroCade exapmple from DesignLab 1.0.8 and enable debug I can see when the 'random' notes occur. I will see the note I play, then an immediate noteoff (even though I didn't release the key) and then the message for a random note nowhere near the one I was playing and no noteoff msg for that random note. I have to press another key to stop it. It happens if I am playing slow or fast, but, 'seems' to occur more often when playing fast because it has more opportunities to show the issue. I'm hoping there is a way to resolve these issues. Seeing how at least one other person is having/had very similar issues I'm think there isn't anything defective with my RetroCade itself, but I suppose that is still possible. I'd rather not have to purchase a new midi controller, but would be open to doing that if it will resolve the issue since I can't use the RetroCade 'stand-alone' with these issues at present. My thanks for any suggestions or fixes for the issues I'm seeing. Best regards, Anthony
  16. Jack, The problem appears to be with creating the bus tap. When it didn't like it, the single bit of the bus tap was connected to vcc. When it did like it, the single bit of the bus tap was connected to one of the 32 bits of the wishbone register (i.e. both sides of the bus tap were connected to the same XLNX_ symbol). Another problem I had was that whenever I would save the schematic after changes, ISE would hang (I am using Lubuntu 14.04) and I had to end the process to gain control again. It does seem the changes were getting saved though, since when I edited the circuit again, I saw the changes. However, when I went into ISE directly and edited the circuit directly instead of pressing the edit circuit button in DesignLab 1.07 to edit the circuit, it would save my changes without hanging ISE. I will keep trying to carry out the experiments you suggested. Regards, Blake
  17. Hi Jack, When I connect wishbone register 1 (0:0) to vcc and then try to synthesize it, it complains with the following errors. Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.xst" -ofn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.syr" Reading design: Papilio_DUO_LX9.prj ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpu_config.vhd" into library work Parsing package <zpu_config>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpupkg.vhd" into library work Parsing package <zpupkg>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuino_config.vhd" into library work Parsing package <zpuino_config>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuinopkg.vhd" into library work Parsing package <zpuinopkg>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/sram_ctrl8.vhd" into library DesignLab Parsing entity <sram_ctrl8>. Parsing architecture <behave> of entity <sram_ctrl8>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/pad.vhd" into library DesignLab Parsing package <pad>. Parsing entity <isync>. Parsing architecture <behave> of entity <isync>. Parsing entity <iopad>. Parsing architecture <behave> of entity <iopad>. Parsing entity <ipad>. Parsing architecture <behave> of entity <ipad>. Parsing entity <opad>. Parsing architecture <behave> of entity <opad>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_to_Registers_x10.vhd" into library DesignLab Parsing entity <Wishbone_to_Registers_x10>. Parsing architecture <rtl> of entity <wishbone_to_registers_x10>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_DUO_V2.vhd" into library DesignLab Parsing entity <ZPUino_Papilio_DUO_V2>. Parsing architecture <behave> of entity <zpuino_papilio_duo_v2>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_GPIO.vhd" into library DesignLab Parsing entity <Wing_GPIO>. Parsing architecture <Behavioral> of entity <wing_gpio>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_DUO_Wing_Pinout.vhd" into library DesignLab Parsing entity <Papilio_DUO_Wing_Pinout>. Parsing architecture <BEHAVIORAL> of entity <papilio_duo_wing_pinout>. Parsing VHDL file "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" into library work Parsing entity <Papilio_DUO_LX9>. Parsing architecture <BEHAVIORAL> of entity <papilio_duo_lx9>. ERROR:HDLCompiler:806 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 537: Syntax error near "=>". ERROR:HDLCompiler:854 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 86: Unit <behavioral> ignored due to previous errors. VHDL file /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf ignored due to errors --> Total memory usage is 111596 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Process "Synthesize - XST" failed WARNING:ProjectMgmt - File /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.stx is missing. Could you tell me what I am doing wrong? I have attached the changed .sch file and generated .vhf file. Regards, Blake Papilio_DUO_LX9.sch Papilio_DUO_LX9.vhf
  18. Hello Blake, Unfortunately I won't get much time to put together an example until next weekend so I will try to talk you through what you need to do. If you look at the image below (from the tutorial) you will see that the Wishbone_to_Registers_x10 symbol exposes the pads for 10 different registers. So anything you connect to them will be readable from your C code on the AVR. In the example below the input is connected to the output, this just means that the registers echo whatever to put in from the C code on the AVR. For your application you will want to remove those wires connecting the inputs to the outputs. Then experiment with connecting VCC and then GND to the register0_in and then verifying that you read back a zero or one from your C code. You can also wire the register0_out to an I/O marker (connected to a physical pin on the Papilio Board) and then verify that you can write to register0 in your code and see the physical pin has the corresponding change. You could then find the example that shows how to make a counter in the schematic editor and implement it and then connect the counters output into the register0_in. One important thing that I just noticed is that each register is 32 bits so it is not as simple as just connecting register0_in to an I/O marker or VCC or GND. You will need to connect those single signals to register0_in(0) or register0_out(0) and read the first bit of the 32 bit wide register. You will want to use a bus tap to accomplish that. There is a tutorial here. Once you get comfortable with doing this from the schematic editor then move on to VHDL. You will want to make a VHDL module that outputs your counter as a port at its top level. Start with making a module that just outputs a 0 or 1 from a port at the top level. After you have created the VHDL module (as a file included in your project) then right click on that file in your file hierarchy list on the left side of ISE and there should be an option to turn the VHDL file into a symbol. Once you successfully run the command to generate a symbol from your VHDL file you should then be able to find it in the symbol navigator and add it to your schematic. Then you connect it to the pads of the Wishbone_to_Registers_x10 symbol. Hope this gets you rolling in the right direction. Jack.
  19. Jack, I ran through the Papilio DUO – AVR to ZPUino Communication over Wishbone example and it worked fine. However, it is not apparent to me how to access these same registers using vhdl. Could you show the changes that would be necessary for vhdl code to increment the register instead of the AVR, in which case the ZPUino code would will still see the register being incremented even if the AVR code was not running. Regards, Blake
  20. In the meantime, try to comment out this section like it says: //Comment out this section for Papilio One. #ifdef __ZPUINO_PAPILIO_PRO__ #include <SD.h> #include "SmallFS.h" #include "modplayer.h" #include "ramFS.h" #include "cbuffer.h" MODPLAYER modplayer; #endif Like this: //Comment out this section for Papilio One. //#ifdef __ZPUINO_PAPILIO_PRO__ // #include <SD.h> // #include "SmallFS.h" // #include "modplayer.h" // #include "ramFS.h" // #include "cbuffer.h" // MODPLAYER modplayer; //#endif
  21. OK, I will try to take a look at this tonight and get back to you. Jack.
  22. Hi Jack, The sketch is in presented on the opening page of the design lab program under “HARDWADE” logicstart. I have not modified the file, It does not say which boards it will or will not work on, although it does have #ifdef __ZPUINO_PAPILIO_ONE__ in the file. Regards, Tony Tony_LogicStart.ino
  23. I have never tried out the ethernet shield with the Papilio DUO so not sure what the problem is that you are running into... If you load a blank circuit to the FPGA side then there should not be any conflicts... You could also try to use one of these types of ethernet modules: http://store.gadgetfactory.net/ethernet-module/ Jack.
  24. Yes, I haven't visited that code in a while but I'm pretty sure what you are running into is that certain libraries are disabled for the Papilio One because there is not enough memory to support them. What are you trying to compile anyway, I can't really tell from your pasted information... It should say in the comments for the example what boards are supported. I think the Papilio One barely supported the Amiga mod player by itself, but definitely not with other players... That was the whole reason for the RetroCade light version. It was made for the Papilio One. Jack.
  25. I could manage to assign IP address to the Arduino ethernet shield mounted on Papilio Duo board, But when I tried to establish communication using TCP/IP, collision was detected by the ethernet shield. I think it must be because of the common SPI bus shared by both AVR microcontroller and Xilinx FPGA. Is there any work-around solution of the problem? I used Ethernet library from Arduino IDE. At present Xilinx FPGA is disabled, but in next stage I will be using wishbone bus shared registers.
  26. Jack, Thanks for getting back, but the error message is regarding a compiler errors relating to file handling, C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:135: error: `FILE' undeclared (first use this function)C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:135: error: `fp' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:141: error: `fopen' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:143: error: `fseek' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:144: error: `ftell' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:147: error: `fread' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:148: error: `fclose' undeclared (first use this function) Error compiling. Do you really think this could be related to a memory issue ? BTW it give the same error on the non-hyperion ZPUINO, Regards, Tony
  27. Not everything will fit into the Hyperion version of ZPUino. Hyperion sacrifices some memory that was available for program space for video memory. The Papilio One does not have any external memory so it is very memory constrained compared to the Papilio Pro. Then Hyperion makes it even more so... I would recommend trying the regular version of ZPUino for the Papilio One and see if it works. If not then the Papilio One does not have enough memory for the example you are trying to synthesize. Jack
  28. I get the following error message when compiling for the papilio one 500, in designlab 1.08 (and 1.07) it works correctly for the papilio pro. Any one has any ideas ? Arduino: 1.0.8 (Windows 7), Board: "Papilio One (500K) - ZPUino Hyperion" Build options changed, rebuilding all Found smallfs directory C:\DesignLab-1.0.8/hardware/tools/zpu/bin/mksmallfs C:\Users\Tony\AppData\Local\Temp\build9072019199683906941.tmp/smallfs.dat C:\Users\Tony\Documents\DesignLab\Tony_LogicStart/smallfs SmallFS: Packed 1 files sucessfully!!! C:\DesignLab-1.0.8\hardware\zpuino\zpu20\libraries\SPI\SPI.cpp:116: warning: unused parameter 'bitOrder' C:\DesignLab-1.0.8\libraries\SD\SD.cpp:320: warning: unused parameter 'object' C:\DesignLab-1.0.8\libraries\SD\SD.cpp:312: warning: unused parameter 'object' C:\DesignLab-1.0.8\libraries\SD\SD.cpp:234: warning: unused parameter 'isLastComponent' C:\DesignLab-1.0.8\libraries\SD\SD.cpp:234: warning: unused parameter 'object' C:\DesignLab-1.0.8\libraries\SD\SD.cpp: In member function `bool SDClass::begin(uint8_t, uint8_t)': C:\DesignLab-1.0.8\libraries\SD\SD.cpp:362: warning: control reaches end of non-void function C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:763: warning: unused parameter 'blockNumber' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:763: warning: unused parameter 'eraseCount' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:713: warning: unused parameter 'token' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:713: warning: unused parameter 'src' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:698: warning: unused parameter 'src' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:659: warning: unused parameter 'blockNumber' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:659: warning: unused parameter 'src' C:\DesignLab-1.0.8\libraries\SD\utility\Sd2Card.cpp:582: warning: unused parameter 'sckRateID' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:1291: warning: unused parameter 'str' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:1276: warning: unused parameter 'b' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:1174: warning: unused parameter 'buf' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:1174: warning: unused parameter 'nbyte' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:667: warning: unused parameter 'v' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:653: warning: unused parameter 'fatTime' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:637: warning: unused parameter 'fatDate' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:608: warning: unused parameter 'dir' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:608: warning: unused parameter 'width' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:210: warning: unused parameter 'flags' C:\DesignLab-1.0.8\libraries\SD\utility\SdFile.cpp:210: warning: unused parameter 'indent' C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp: In function `pt_mod_s* pt_load(char*, int)': C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:135: error: `FILE' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:135: error: (Each undeclared identifier is reported only once for each function it appears in.) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:135: error: `fp' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:141: error: `fopen' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:143: error: `fseek' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:144: error: `ftell' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:147: error: `fread' undeclared (first use this function) C:\DesignLab-1.0.8\libraries\modplayer\ptplay.cpp:148: error: `fclose' undeclared (first use this function) Error compiling. Regards Tony Smith
  29. actually, if its a sensor, shouldnt you just be able to set the chip to receive mode and not even bother with writing to it other than once (or just pull the pin LOW) then just listen to the receive in a loop?
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