Stabilize a camera mounted on a flying machine
Locking a ground target to shoot
Locking a flying target for filming
Here is an image that explains the system principle:
Check out Laurent's documentation for an in-depth look at what went into this project and watch some nice demonstration videos of the system in action.
I was musing over it all day and decided to give it a try.
There I was feeling extra clever at how well it works, and upload the a video of it in operation to Youtube. As soon as it finished it recommends that I might want to watch another video - it is somebody transmitting music on FM using only an FPGA. I don't feel so clever now!
Original forum thread.
What is it? its the standard romgen.exe by mikej included with the Arcade Blaster application, but with a twist. (source released with mikej's permission)
by including the -ini switch on the command line, it is capable of doing some simple bitswaps on the raw ROM data allowing various other games to run on PacMan hardware.
Currently I have ini / batch file combinations for the following :
shoot the bull
pac-man plus (currently the only ini uploaded to github)
since they are based on the pacman hardware with some simple address lines switched around.
other encryption types can easily be supported and the ini files are created by using information
found in MAME.
In the coming days, i will update the git repository with the other ini and bat files, and of course
proper documentation that shows how to use it.
maybe at some point, we can get support for the -ini switch added to arcade blaster for native support.
Switches control LED's
A mod file is played out the audio jack
An arcade graphic is displayed on the VGA output using the VGAZX video adapter
Joystick controls counters on the 7-segment LED
Analog is measured and displayed on the 7-segment LED
The Analog input is not working on properly on all channels.
This only works on the Papilio One 500K right now, we have not generated a bit file to work on the Papilio One 250K yet.
Quick Test by loading the merged Bit File to the Papilio One 500K
Download the latest bit file from the download page.
Use the Papilio Loader to program the bit file to SPI Flash.
Load the sketch using the ZPUino IDE.
Download the latest version of the Papilio Sketches from Github.
Unzip and navigate to ZPUino\LogicStart_QuickStart
Load the ZPUino Soft Processor LogicStart VGAZX variant to the Papilio
Use the Papilio Loader to load bit_files\zpuino-1.0-PapilioOne-S3E500-LogicStart-VGAZX.bit to SPI Flash.
[*]Make sure the latest version of the ZPUino IDE is installed.
[*]Open LogicStart_QuickStart.ino with the ZPUino IDE.
[*]Choose the correct board
ZPUino on Papilio One (500) board
Choose the correct Serial Port
Press the "Upload" icon
For more information about getting started with the ZPUino IDE.
I've just finished my 8 digit frequency counter - I'm just waiting for a GPS module to arrive so I can use it as the reference timesource.
Here's a block diagram of the project:
And here is a photo of it in action, when using a one pulse per second generated from the local Xtal as the reference.
Full source is up on my wiki at http://hamsterworks....equency_counter
Finally! PCB goodness in them mails. Feels like xmas.
First off I assembled the super easy Papilio HDMI wing, You can see different views of it in the insets as well as how it fits on the Pap board. It is technically not an 8 bit wing nor a standard 16 bit wing but a kind of modified 16 bit wing as it straddles two 8 bit wing slots due to the requirement for differential pins. The row of 4 pins with the missing pin connects to power and ground, the next row of 8 pins connects to the standard 8 bit wing and finally the last row of 4 pins connects to the adjacent 8 bit wing's pins to get to the differential pair's other pins which are not available on any 8 bit wing alone.
Next filing the PCB corner to make it fit in the oddly shaped space and line up with the screw holes.
Finally (for today) assembled the PCB with the tiny 3.3V switch mode power supply regulator, the pot for adjusting the LCD brightness and the HDMI connector where the LCD differential pins will connect to.
The only testing was to apply power to the board above and check that I get 3.3V which initially I wasn't. This is what happens when it takes a month from designing it until the PCBs arrive. Going back to the schematic I quickly realized I had made a decision to only enable the switch mode supply when the input voltage exceeds 9V (this can be easily changed as it's only a resistor divider) and I was only supplying 8.5V. Quick turn of the knob on the lab PSU to bring the input voltage above that threshold solved the problem and I could measure 3.3V on the output.
Next, I have to start cutting into the LCD plastic enclosure to open up spaces for the connectors and the pot which will protrude out the front of the LCD panel. Not really looking forward to that, cutting into plastic and making precisely aligned openings is not my favourite activity.
OK it's nearly 2am and I'm off to bed... satisfied I have accomplished the task I set out to complete
After much cutting the plastic case with a box cutter and a metal nibbler and drilling holes I finally had the mechanical side sorted. Finished soldering the wires to the board and hooked it all up to the Papilio then run a quick LVDS test and... nothing. No picture at all. I immediately thought, oh crap, SI issues (signal integrity). How can this be, after all it used to work with just loose wires flying about. Is it the the HDMI wing, is it the trace width, is it the trace spacing, impedance issues? All these thoughts and more run through my head, but as always, one must approach a seemingly unsolvable problem one step at a time.
I checked the power in and out of the switch mode supply, all good, checked the noise on the output, not all that great, about 100mv of a square looking ripple at about 6.6Mhz. Hmmm... whatever.
Checked the trace continuity from the Papilio HDMI wing all the way through the HDMI cable to the panel pins. This is where I uncovered a problem. One of my signal pairs was not coming though. This turned out to be because I had a soldering issue with two of the pins on the HDMI connector on the panel side, they were not making contact with the PCB traces. A quick touch up with the soldering iron fixed that, so after rechecking all signals for continuity I was all cocky thinking I had my issue licked. But alas, on testing, still no picture on the panel. On with the troubleshooting.
Next it was time to check the HDMI wing so off to synthesize Mike's DVID test, but first I must adapt it to the Papilio by creating a suitable ucf file. With ucf done and project flashed on the Papilio I hooked up the HDMI wing to a HDMI monitor and two things became immediately apparent. I had a picture which was great. The quality was not perfect which was not so great. There were a few visible artefacts and I guess that is to be expected since the signal path from FPGA to HDMI connector was not really designed with high speed signals in mind or even matched traces.
At least the HDMI wing was tested to be OK. It was about at this stage when it hit me that while creating the ucf file before, I had a niggling feeling that some signals to the LVDS panel were in a different order. I double checked my LVDS driver project and sure enough that was the case. Initially, a month ago, I had tested the panel with wires soldered directly to a header that plugged into the Papilio expansion header but when I designed the HDMI wing I followed the HDMI pinout. Because of that, some of the differential signals had been swapped around, eg my panel clock now connected to one of the signals... so after fixing up the ucf to match the correct pins, I finally had a picture on my panel.
With the cover screwed in, it looks like this. I should mention at this point that the pot intended to control the brightness, doesn't. I had honestly thought after checking the datasheet for the CCFL driver that the brightness would be controlled by an analog voltage, but it seems that chip has a few different modes, depending on how three of its pins are wired. Two of the modes are analog brightness control (on different pins) and the third mode is PWM brightness control. It would appear this is the case here. So the pot when turned all the way to one side turns off the backlight, then as it is wound up, when the analog control voltage reaches 1.5V it turns the backlight fully on. Oh well, I can live with that If I was bored, I'd attempt some circuit surgery on the CCFL driver board to rewire the pins and change the mode to analog but that's not a huge priority for me right now.
Final picture of the complete project. I should really remind you again that just because the panel has been fitted with an HDMI connector, it DOES NOT have the smarts to recognize TMDS encoded HDMI signals, it needs to be driven with LVDS.
I came across that SVF filter at that site a while ago and (after of course translating it to VHDL) I promptly expanded the test jig with more input waveforms and implemented all filter type outputs. So as inputs I can select noise, sqware, sine and sawtooth and for outputs I can select lowpass, bandpass, highpass and notch (band stop).
I dug up the test code and made a
to show what it can do. The parameters of the filter are, fsample=800Khz, Q=1 and you can clearly see that even at Q=1 it still amplifies the signal at the filter's cut off frequency. Due to the internal number representation use I cannot lower the Q any more and of course increasing the Q will cause even more amplification to the point of overdriving the output (causing math overflows).
I just uploaded a small video demoing Linux running inside ZPUino (simulator).
Things are really going smooth. Now, hardware must be slightly adapted in order to achieve a "decent" performance.
ZPUino running Linux 3.4.0 (uclinux/Linux MMU-less) with uClibc 0.9.29 and busybox 1.20.2.
My design only requires me to perform some I2C writes to initialize a couple of devices. After trying several different methods and being new to FPGA in general I found that this solution was even simpler than implementing PicoBlaze.
To define the I2C writes performed look inside SimpleI2CCore.vhd where you will find an array called seq:
constant seq: seqT:= (
-- RESET CAM
(const, TCM_DEV_ADDR & '0'),
(const, VIDEO_ENCODER_ADDR & '0'),
Change the const values to the appropriate ones for your device(s). In the attached project there are several writes defined for two different devices, you can remove/add as many as you like just always ensure your last value is idle so that it releases the SCL and SDA lines. Also note the device address constants are 7 bits.
Remember to modify the top boundary of the array here:
type seqT is array(0 to 41) of i2cT;
With a 24Mhz input clock, it produces a 100KHz I2C clock. The additional DCM in the attached project that provides 27MHz is only to drive the external I2C devices and can be removed or modified as needed.
Live output from Papilio:
Hopefully others will find this as useful as I did
Source Code: SimpleI2C.zip
My goal is to provide a full Forth system, that allows the control and programming of FPGA projects through a UART console, without taking too much of the FPGA resources. Forth is good for that because it is very simple, produces very compact code (99% calls to subroutines) and allows the on-the-fly compling of new code on a live system.
To keep things small and fast, I designed a custom processor, with two stacks and only two general purpose registers, with a simple, RISC-like, machine code. The "machine" itself is very small (~7% of a Papilio 500), and uses only 3 ram blocks (1 for stacks, 2 for program/data memory) It seems to work fine, except for the custom UART, which is still a bit buggy (timing problems -- a shame at 9600 bauds...)
It's designed to be easily extensible, using memory mapped devices, so you can use it as an interface to your cores.
The Forth system itself is still very beta, but you can already define words and do some simple arithmetic and io. I implemented a basic "compiler/assembler" and a simulator (both in Java).
Next steps are 1) complete the Forth system and 2) debug the thing thoroughly so it can be used seriously. V0 is on GitHub, at https://github.com/b...9/Papilio-Forth
And more info on Forth on http://www.softsynth...rth/pf_tut.php.
Spin the Wings A+B connector block around 180 degrees, and you should have access to everything but the LEDs and slide switches, plus 16 pins of I/O.
Plug the WIng B pins into the WingC socket and have VGA, Joystick, audio and 32 pins of I/O.
Of course you have to update your UCF files. Here is my updated UCF file for using the Switches and LEDs - Please note I number my LEDs wth LED0 on the right and LED7 on the left - the opposite way to the silk screening!
# LogicStart Megawing with Wing C only plugged into the Wing B socket
NET switches(7) LOC = "P85" ;
NET switches(6) LOC = "P83" ;
NET switches(5) LOC = "P78" ;
NET switches(4) LOC = "P71" ;
NET switches(3) LOC = "P68" ;
NET switches(2) LOC = "P66" ;
NET switches(1) LOC = "P63" ;
NET switches(0) LOC = "P61" ;
NET LEDs(7) LOC = "P58" ;
NET LEDs(6) LOC = "P54" ;
NET LEDs(5) LOC = "P41" ;
NET LEDs(4) LOC = "P36" ;
NET LEDs(3) LOC = "P34" ;
NET LEDs(2) LOC = "P32" ;
NET LEDs(1) LOC = "P25" ;
NET LEDs(0) LOC = "P22" ;
To be totally honest, p&r chockes on some paths, and there are some glitches: the most triangle intensive lines shows some "holes" (you can see through the surface because some triangles were not drawn), and some lines edges spill ouside the triangles. The latter might be caused by fixed point arithmetic (for very flat triangles) or the failing timing constraints.
Again, I cannot attach the bit file, but it's on github (final.bit)
Full forum discussion thread.
The panel requires about 10V (5W) for the CCFL inverter and 3.3V (1.4W) for the logic, you can see below a 3.3V linear regulator I found in my junkbox bolted to a heatsink which I'm using currently do bring up the LCD panel. Additionally the panel is driven with four LVDS differential pairs, three for data and one for clock.
Currently I have all the signals soldered to a small perfboard with a header that plugs into wing slots BH and AL. The reason I chose these slots is because I need differential signal pins and no single wing alone provides these.
Eventually I plan to make a small circuit board with a switch mode regulator that will fit in the corner seen in the picture above (the three screw holes). The PCB will have a barrel connector for power, a small pot for adjusting the brightness and a HDMI connector for the signals. Below is an eagle board I submitted to Batchpcb the other day. The LCD panel is not HDMI capable but the HDMI connector is ubiquitous and ideally suited for passing the high frequency data signals required.
On the right hand side above is a Pap wing with an HDMI connector which I plan to use to connect to the LCD panel but by reprogramming the FPGA to talk TMDS, that wing should be able to be used with any proper HDMI sink. I can't wait to use that wing to try out Mike's Dvid_test on my HDMI monitor.
The ground planes in the picture above have not been rendered for clarity. I've already received the components from Digikey (in less than 2 days no less) but Batchpcb has been having issues for the last few days and I only just today managed to buy my design, now a few weeks waiting for boards to turn up
It plays Brahms Lullaby in monophonic glory! One pair of switches changes between a Sine wave and a richer waveform I made in a spreadsheet. Other pairs control the envelope (Attack, decay and release rates). I'm thinking of using the ADC on the LogicStart to give me analogue control inputs...
It only 'does stuff' one clock cycle in 666 of the 32MHz clock, so there is plenty of scope to move to direct digital synthesis or massive polyphony.
Buried on the related pages are the C utilities to convert arrays to either 9 or 18 bit BRAM VHDL instances...
Full discussion thread
VGALiquidCrystal Wiki Page.
Get started with the ZPUino "LogicStart" bit file.
Virtual 7 Segment Wiki Page
Virtual 7 Segment Source Code on Google Code
Main Github page.
Download the bit file.
VGA library reference is here.
Source code for the LogicStart variant.
Get Started with the ZPUino.
* 16 channels
* 1024 samples
* Requires only one I/O pin - or no pins if your Dev board has a USB to RS232 interface
* Light on resources - one Block RAM and about 100 slices.
I've made a very simple character mode user interface for use under Linux. It is functional but not flash. It is not as good as the Vendor's VLA as it needs to be added to your design it is built, but it works a treat.
It's all up on my Wiki at http://hamsterworks.....php/CheapScope
If (like me) you don't run Linux natively you can always use Virtual Box's USB device pass-through, allowing your VM to see the USB-to-Serial device.
- unzip the archive, it the source project,
- install srecord and z88dk (on ubuntu, the stock packages works fine)
- type "make rom.o" => you get the binary for the code, you can put it in place of the original code rom in your pacman papilio bit file (use the same roms for graphics and sound).
to try it with mame :
- grab your favorite mame roms for "puckman" (google is your friend there)
- unzip it into the puckman directory (actually, you do not need the namcoxxx roms, as they will be overwritten)
- install mame, of course,
- the 'from source' debug version of mame I use reads the provided mame.ini file and runs fine from the "tetris" dir, but if your mame complains, you'll want to add a pointer to the project directory in the right config file
- patch the paths in the makefile,
- type "make" and enjoy
note 1 : controls are obvious except for the "rotate" command, which is mapped on "up" (no button on pacman...)
note 2 : the C code should be readable, although I have not spent hours commenting it. You can have a look at the crt0.asm file if you are curious : it's very crude, only what is needed for zd88dk to work is included.
To have a complete devkit for the pacman machine, we will need a graphics/palette editor... the sprite format is quite straightforward, so it should be easy to at least make a bmp=>rom converter
Source code is in the attachments
View attachment: tetris.zip
So the only option left was to make my own board - basically merging the fpga and LPDDR from the LX9-Microboard with the formfactor, wing interface and tool-set from Papilio, then adding all the needed interfaces on-board (and then some more to make it more interesting). The biggest challenge was the 324-ball BGA package which forced me away from the hobbyist PCB vendors (like Seeed studio and OSH Park) to the more traditional (and expensive) PCB vendors that offers the PCB geometry needed for this board (5 mil trace width/spacing, 8 mil holes, 4-layes).
In my professional life I have used PCB Universe (http://www.pcbuniverse.com/) for many boards with great success and they have very reasonable prices and an on-line quote and ordering system so it's easy to place an order (disclamer: I have no business interest in PCB Universe, just a happy customer). The quote for this board was $450 for 50 boards, more than I like to spend but still a bargin compared to other options.
So far all circuits on the board have been tested OK except for the USB host interface which really need Linux up and running first. The board came out perfect - no cuts or jumpers needed so far.
Read more about the board features here:http://pipistrello.saanlima.com
My plan is to make this an open-source project once all features on the board have been verified.
One of the problems with extending the AVR softcore is that it just didn't seem to be built for a peripheral rich setup (IO space, etc). But I didn't want to leave an open source GCC based solution. Which is why I've watched the ZPU work with interest.
I recently tried to use a quadrature interface from opencores, but it was far too featureful and resource heavy.
So instead, I created my own "simple" quadrature interface for the ZPU, and using the standard HD44780 code in the ZPUino IDE install, created a sketch to read the quad counter and write to the LCD.
It is so very nice to read a quadrature encoder as simply as:
unsigned int y=REGISTER ( IO_SLOT (8) ,0);
And to know that it is being clocked at 96Mhz.
(Of course, I most probably have created a piece of junk, full of bugs - but I think it's cute)
The code's a complete mess, but if you're interested... it's attached.
View attachment: ZpuQuadDec.zip
You can find the details of my project (incl all the vhdl source) here: http://hamsterworks....x.php/Dvid_test
Feel free to use it in your own projects. Wonder if it will work on the Papilio Pro? Might have to butcher a cheap HDMI cable...
This post was covered on Hackaday too.
Generates a text display
Glorious 3-bit Color Output
Hardware Cursor (with selectable style)
Completely Scalable Design
The controller can be reconfigured via a few constants
Many different VGA resolution standards may be selected
Different fonts can be selected
All logic and RAMs are inferred
Source Code Files : vhdlnerd-vgaDemo-23dbd27.zip
The TV Wing used here is based on an existing design that was made by Papilio user Ben and it is posted on the Papilio Wiki under Wing Playground.
Wicked has made some modifications on Ben’s design to bring the DAC up to 8 bit resolution and using 100ohm/200ohm values for R/R2 and he added some VHDL to convert the cameras YUV422 data stream into the separate Y, U and V channels for encoding.
He also designed a wing to wrap everything up, check out the original forum thread here if you want to read the whole thing and take a look at these designs.
Awhile back I was playing with a CS4954 Video Encoder. It's a great little chip, inexpensive, supports NTSC/PAL, S-Video, SCART, etc via 6 on board 10-bit DACs.
Here is my NTSC/PAL breakout board:
It runs off 5V or 3.3v and requires a 27MHz clock. The interface is via 8bit parallel bus or I2C. If you use I2C, the 8 bit parallel I/O bus becomes an 8 bit GPIO! The pixel data is fed to it via a dedicated 8 bit bus. Using I2C you basically get these I/O lines back with the GPIO.
It supports both Master mode where it will supply the vertical and horizontal syncs or Slave where those signals are provided by the host device.
I have seen some cool things done with this chip in the 6502.org forums with FPGAs and was curious if anyone would like to help me get some VHDL going on Papilio for this thing. I have the i2c start up sequences to get output running and have drawn some simple patterns with it using an Arduino, but that's about it.