FPGA Discussions

Ask FPGA questions, share FPGA knowledge.

110 topics in this forum

  1. SDRAM controller with consistent access time?

    By Matthew Hagerty,
    • 33 replies
    • 8,678 views

  2. Simple Pulse Generator outputting pulse groups instead

    By MamboDee,
    • 6 replies
    • 2,051 views

  3. snickerdoodle $55 Open Source ZYNQ board on crowdsupply

    By nilrods,
    • 13 replies
    • 3,661 views

  4. so what about dsp slices then

    By Chris_C,
    • 6 replies
    • 5,743 views

  5. Software tools

    By Guest godfool,
    • 5 replies
    • 693 views

  6. Software/Hardware

    By luisfpl,
    • 1 reply
    • 664 views

  7. Source control / ISE

    By jbb,
    • 2 replies
    • 1,776 views

  8. SPI to initialize TFT

    By james1095,
    • 7 replies
    • 1,921 views

  9. Starting with FPGA

    By Nishant Sood,
    • 11 replies
    • 1,465 views

  10. TCE (TTA based Co-design Environemnt)

    By OmniTechnoMancer,   
    • 1 reply
    • 647 views

  11. This is amazing!

    By Jack Gassett,
    • 3 replies
    • 667 views

  12. Timing constraints

    By jbb,
    • 2 replies
    • 551 views

  13. To Remove Debounce from MicroJoystick installed on LogicStart MegaWing (FPGA) and read input correctly

    By Kanupriya,   
    • 2 replies
    • 1,132 views

  14. UART with Papillio One FPGA board

    By falcon,
    • 0 replies
    • 123 views

  15. Unclocked processes

    By alex,
    • 4 replies
    • 761 views

  16. USB to ps2

    By Chris_C,
    • 4 replies
    • 1,157 views

  17. Using FPGA - Am I right to do so?

    By truni,
    • 16 replies
    • 1,936 views

  18. Using IP cores in designs.

    By hamster,
    • 3 replies
    • 781 views

  19. VDHL signal module question

    By nilrods,   
    • 4 replies
    • 994 views

  20. Verilog Code Question from J1.v Papilio-Forth

    By craiglindley,   
    • 2 replies
    • 1,092 views

  21. vga controller gottcha...

    By Chris_C,
    • 5 replies
    • 770 views

  22. VHDL newbie: 'if' on a process sensitivity list element

    By flag26838,
    • 12 replies
    • 2,723 views

  23. vhdl problem with testbench

    By sam,
    • 1 reply
    • 999 views

  24. VHDL processes

    By Myndale,
    • 2 replies
    • 991 views

  25. vhdl/xilinx ise questions: reusing chip code, automatic log() of generics and a PULLUP warning

    By flag26838,
    • 3 replies
    • 1,318 views