FPGA Discussions

Ask FPGA questions, share FPGA knowledge.

109 topics in this forum

  1. FPGA... what for?

    By F6EEQ,
    • 5 replies
    • 5,565 views

  2. Affordable Xilinx UltraScale+ Kintex dev board on CrowdSupply

    By agilmine,
    • 1 reply
    • 116 views

  3. FPGA to AVR (or cheap FPGA) comms

    By tim minke,
    • 0 replies
    • 57 views

  4. SPI to initialize TFT

    By james1095,
    • 7 replies
    • 1,394 views

  5. FPGArduino - where FPGA meets Arduino - FER

    By mistery,   
    • 8 replies
    • 2,485 views

  6. Artix 7 1080p HDMI / timing constraints

    By papry,
    • 0 replies
    • 497 views

  7. Delta Sigma Feedback Question

    By Chris Wilcox,
    • 0 replies
    • 414 views

  8. VHDL processes

    By Myndale,
    • 2 replies
    • 865 views

  9. Implement an IIR into my FPGA project

    By Brightstars,
    • 0 replies
    • 560 views

  10. data_valid pattern?

    By keesj,
    • 1 reply
    • 416 views

  11. What is the best way to control RS485?

    By Yeezy,
    • 3 replies
    • 2,510 views

  12. Interfacing memory to papilio fpga board

    By kyson,
    • 1 reply
    • 440 views

  13. OV7670 vhdl code.

    By ahmt_cetin,
    • 3 replies
    • 1,308 views

  14. Yet another VHDL CPU core

    By alex,
    • 6 replies
    • 4,122 views

  15. RAM device / timings for small VGA project

    By kyson,
    • 5 replies
    • 700 views

  16. Need little help to Implement this Virtual 7 Segment display on VGA

    By Haider,
    • 17 replies
    • 3,300 views

  17. Using FPGA - Am I right to do so?

    By truni,
    • 16 replies
    • 1,778 views

  18. arty $99 artix fpga board

    By nilrods,
    • 17 replies
    • 3,727 views

  19. CVSD decoder

    By james1095,
    • 6 replies
    • 1,570 views

  20. newbie: unstable signal, delay, or what else?

    By flag26838,
    • 1 reply
    • 809 views

  21. snickerdoodle $55 Open Source ZYNQ board on crowdsupply

    By nilrods,
    • 13 replies
    • 3,475 views

  22. newbie: why is taking 2 clock cycles to update the output? AKA are statements inside a process() block really sequential?

    By flag26838,
    • 4 replies
    • 699 views

  23. Cubic Board FPGA

    By nilrods,
    • 9 replies
    • 2,195 views

  24. VDHL signal module question

    By nilrods,   
    • 4 replies
    • 887 views

  25. Altera Intel impacts

    By nilrods,
    • 12 replies
    • 1,827 views