FPGA Discussions

Ask FPGA questions, share FPGA knowledge.

110 topics in this forum

  1. FPGA... what for?

    By F6EEQ,
    • 5 replies
    • 5,766 views

  2. UART with Papillio One FPGA board

    By falcon,
    • 0 replies
    • 245 views

  3. Affordable Xilinx UltraScale+ Kintex dev board on CrowdSupply

    By agilmine,
    • 1 reply
    • 329 views

  4. FPGA to AVR (or cheap FPGA) comms

    By tim minke,
    • 0 replies
    • 187 views

  5. SPI to initialize TFT

    By james1095,
    • 7 replies
    • 2,449 views

  6. FPGArduino - where FPGA meets Arduino - FER

    By mistery,   
    • 8 replies
    • 3,053 views

  7. Artix 7 1080p HDMI / timing constraints

    By papry,
    • 0 replies
    • 998 views

  8. Delta Sigma Feedback Question

    By Chris Wilcox,
    • 0 replies
    • 649 views

  9. VHDL processes

    By Myndale,
    • 2 replies
    • 1,159 views

  10. Implement an IIR into my FPGA project

    By Brightstars,
    • 0 replies
    • 748 views

  11. data_valid pattern?

    By keesj,
    • 1 reply
    • 573 views

  12. What is the best way to control RS485?

    By Yeezy,
    • 3 replies
    • 4,132 views

  13. Interfacing memory to papilio fpga board

    By kyson,
    • 1 reply
    • 565 views

  14. OV7670 vhdl code.

    By ahmt_cetin,
    • 3 replies
    • 2,467 views

  15. Yet another VHDL CPU core

    By alex,
    • 6 replies
    • 4,525 views

  16. RAM device / timings for small VGA project

    By kyson,
    • 5 replies
    • 1,011 views

  17. Need little help to Implement this Virtual 7 Segment display on VGA

    By Haider,
    • 17 replies
    • 3,842 views

  18. Using FPGA - Am I right to do so?

    By truni,
    • 16 replies
    • 2,083 views

  19. arty $99 artix fpga board

    By nilrods,
    • 17 replies
    • 4,131 views

  20. CVSD decoder

    By james1095,
    • 6 replies
    • 2,420 views

  21. newbie: unstable signal, delay, or what else?

    By flag26838,
    • 1 reply
    • 960 views

  22. snickerdoodle $55 Open Source ZYNQ board on crowdsupply

    By nilrods,
    • 13 replies
    • 3,868 views

  23. newbie: why is taking 2 clock cycles to update the output? AKA are statements inside a process() block really sequential?

    By flag26838,
    • 4 replies
    • 875 views

  24. Cubic Board FPGA

    By nilrods,
    • 9 replies
    • 2,436 views

  25. VDHL signal module question

    By nilrods,   
    • 4 replies
    • 1,078 views