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  1. Yesterday
  2. Gregg

    Newbie Programming 3 Questions

    Bnusbick, Many thanks for the pointer. I was wondering HOW I flash the SPI and you've answered that question. I want to move to the 2.8 loader as soon as I can.
  3. Spotted something on Ebay UK and though others might be interested. "Papilio Pro FPGA with Arcade Megawing (Xilinx Spartan 6)" but it now @ £64.99. Seems good value to me. Note: I have absolutely no connection with the seller. Out of interest I searched for "Papilio FPGA" on Amazon UK. "SeeedStudio Papilio Duo-2Mb Fpga On The Top Atmega32U4 On The Botom DIY Maker Open Source BOOOLE" @ £188 ($245). Ouch! "Papilio Duo-2Mb" @ £201 ($262). ...and various other overpriced Papilio related boards.
  4. bnusbick

    Newbie Programming 3 Questions

    By the way, I am using Papilio Loader 2.8.
  5. bnusbick

    Newbie Programming 3 Questions

    Hi Gregg, I don't have the Pro, but do have the Papilio One 250 and Papilio Duo. I use papilio-loader-gui to program them in Linux. In the lower part of the menu, it has the header 'Operations'. I currently have 'Scan', 'Erase', 'Write to', and 'Verify' checked. Underneath 'Write to' there is a drop down menu. I select 'FPGA' for temporary changes, and 'SPI Flash' if I want it to retain the changes after a power cycle.
  6. Last week
  7. Hi all, Questions at the bottom of the post.... I've got a Papilio Pro which I'm running on an Unbuntu 16.04 64 bit system. I've installed the 2.5 version of the Papilio Loader. (I know 2.8 is out there - have questions but that's another post). I'm using the USB -> micro USB cable to connect the Pro to my Linux Box. When I first powered the Pro up (by plugging it in), LED1 blinked at about once per second. I have read that the Pro comes with that configuration programmed into the non-volatile memory so I wasn't surprised. From the web, I downloaded this .bit file: http://papilio.cc/sketches/Quickstart-Papilio_Pro_LX9-v1.5.bit Using the papilio loader I loaded the file into the FPGA and observed the results - it worked. I can see the output ascii table. Also the LED1 blinking stopped (no surprise). If I then unplug the Pro....and plug it back in, the LED1 starts blinking again. Question 1: When I download the .bit file to the Pro, I am programming the volatile memory - is that right? Question 2: If so then the LED1 blinking configuration is in the non-volatile RAM and that gets installed int he Volatile RAM at power up. Do I have that right? Question 3: Where do I go to read up on how to program the non-volatile RAM? Thanks
  8. flag26838

    Logic Megawing SSEG display part number

    Uhm, good question, probably only @Jack Gassett can help you here.
  9. I'd like to use a LogicStart Shield with a basic 5V Arduino UNO to use for early S/W design of a digital clock for a High School STEM program I am teaching. We need a 7-Seg display and some switches to set the time, timer, and mode of the clock. It looks like the slide switches would be fine but will the 7-Segment AN drivers be OK driven by 5V Arduino UNO outputs? As I recall, some of the individual LEDs have limiting resistors on the DUO so I'll stay away from driving those. Thanks, -Chris
  10. Hi Teaching Digital design and fpga we have enjoyed the easy integration with Xilinx ise. Now students find the webpack ise installation link leading to a VM installation. Is the non-VM installation still available ? What would be the preferred installation setup with the ISE in VM ?
  11. Earlier
  12. This question has already been asked but not for a very long time. Given the long time since the last discussion, I would hazard a guess that both have had major improvements. To which I ask which is the best out of the two? I will be using the board as an introduction to FPGAs as I have developed a keen interest in them as of late. As a theoretical physicist I never really encountered any electronics but an FPGA programmer at work gave me a CPLD to play around with after spending a few months of learning electronics. As such I already know a little about VHDL and could probably shift to Verilog without much fuss. The project I am thinking of doing first is to make the FPGA into a logic analyser for other project testing. tech news free netflix I know the Papilio has this feature as standard but given I want to make the project myself that doesn't really matter. What I want to know is, is the I/O routing on the Mojo good enough to allow the 100/200 MHz speeds the Papilio can reach? The Mojo is much easier to get hold of here in the UK whereas the Papilio would have to be imported. That being said the Papilio does have a bundle for everything to make it into a logic analyser (5V buffer boards and test clips) and I guess code which already works out of the box. PS: I would also appreciate any tips for getting a job in FPGA programming as a physicist given that the usual path would be for an electronics engineer. I am only a hobbyist yet but wouldn't mind having the option of my hobby becoming a career. I have already messed around with PICs and CPLDs with reasonable success.
  13. Hi, Is it possible to control the COL-A and COL-C? The schematics for the Logic Megawing is not clear on this (and the ucf does not contain this information either)
  14. Jose de Arimatea

    SDRAM chip model

    Could you share your Verilog controller please?
  15. Jose de Arimatea

    VERILOG SDRAM controller for Papilio Pro

    I'm writing a Verilog controller for this board. Does anyone want to help? I'm having some issues and it is not working yet: https://bit.ly/2GaBwRj
  16. LambdaPI

    Computer doesn't recognize FPGA

    I recently was using my Papilio One and was erasing the spi flash using the papilio loader, when it disconnected and now it doesn’t show up when I try to upload a program. I tried reinstalling the drivers, but that didn’t work. I also installed the papilio loader on a different computer, and it as well didn’t see the board. The board, with the program that was already there, works fine, but I cannot upload anything new to it, since the computer can’t see the board.
  17. Jaxartes

    VERILOG SDRAM controller for Papilio Pro

    Maybe. I don't know of one exactly. Here are some I do know of: Hamster (Mike Fields) wrote one that's been used on the Papilio Pro. But it's in VHDL not Verilog. And the links to his site aren't working tonight. Here's a thread discussing it: http://forum.gadgetfactory.net/topic/2551-hamsters-sdram_controller/. And here's one self contained project which used the controller: http://sowerbutts.com/socz80/. Here's an SDRAM controller written in Verilog, but it's for a different chip than the one used in the Papilio Pro: https://opencores.org/projects/sdram_16bit. I've got one, Verilog for Papilio Pro; but it didn't work. I gave up on it in April 2016. There are probably others, if you search. One that's in VHDL, not Verilog, might still be understandable enough to help you. One that's for a different SDRAM chip might still help you learn something.
  18. flag26838

    Logic Megawing SSEG display part number

    Thanks, that appears to be the correct part number, now i just have to find it at a decent price... the 7ssegs on my logistart is toasted and i wanted to swap it.
  19. Hi, I scanned the forum and saw the following thread: http://forum.gadgetfactory.net/topic/1439-ghosting-on-logicstarts-seven-segment-display/?tab=comments#comment-9086 which has a link to the following: https://www.sparkfun.com/datasheets/Components/LED/7-Segment/YSD-439AY2B-35.pdf which says Model No.: YSD-439AY2B-35. I can't guarantee this is the part number, but it has 8 leads on each side, which matches my logicstart megawing.
  20. What's the part number of the SSEG display employed in the logicstart megawing?
  21. Jose de Arimatea

    VERILOG SDRAM controller for Papilio Pro

    Hi guys, I'm studying how to make my own SDRAM controller. I would like to study a Verilog controller for Papilio Pro to learn. Is there any Verilog SDRAM controller for Papilio Pro that I can check ? Thanks in advance!
  22. papry

    Changing the clock frequency

    Just a quick comment that to generate a slower clock, a preferred method is to use a synchronous counter. This type of counter has all counter flops clocked by the same high speed input clock and fits well with the way that FPGAs handle clocks. It is also the way that this type of circuit would be designed in an ASIC. Here is some code I wrote recently (as an example). It divides 315MHz from a PLL to 3.57MHz. A divide by 88 is required. reg [6:0] pll315_counter; reg clk357; // create 3.57MHz NTSC clock by dividing 315MHz by 88 always @ (posedge w_clk315) begin clk357 <= (pll315_counter<7'd44); if (pll315_counter==7'd87) begin pll315_counter <= 7'b0; end else begin pll315_counter <= pll315_counter + 7'b1; end end You would need to change the counter length, termination count and half count to suit your frequencies. I should have really used constants (such as tick defines) rather than hard code numbers, but hey this is my personal hobby project 😃
  23. silvestru

    Papilio one 100k quick start bit file

    Hi James, Thanks for your reply. I re-positioned the picture by setting the VGA_Invert.vhd constant Horizontal & constant Vertical variables settings. Thanks for the website you recommended. I will try to understand something there.
  24. james1095

    Papilio one 100k quick start bit file

    I'm afraid I can't be much help there, I never tried to invert the video, I've always just left it whichever way the original game was. Most arcade hardware has the ability to flip the screen for cocktail mode though so it should be a matter of just inverting whatever signal controls that in the game to flip the screen. Are you sure the monitor isn't just adjusted so that text is off the screen? I highly recommend reading Free Range VHDL http://freerangefactory.org/ It's free and was a big help to me when I was starting out. You will really need to learn VHDL (or Verilog) in order to get much out of your FPGA board, using only existing projects without being able to modify them is extremely limiting, once you know a bit of VHDL you can understand how they work and tweak things as needed.
  25. mchowder

    Changing the clock frequency

    I asked around and realized that having the clock go through an inverted d flip flop divides the clock in half. I need 23 flip flops much like your 23-bit counter Thank You!
  26. silvestru

    Papilio one 100k quick start bit file

    James, thanks for replying. I don't think it's part of the project. As you may already know I am new to this FPGA thing. I downloaded it many times from GitHub and managed to make both Pacman and Space invaders work. The problem was that they are opposite to each other on the screen and you have to turn the monitor the other way round. Then I saw a thread on the forum named Video inversion for Invaders for space invaders by Marco. The problem was I could not create the u_invert file for it. But finally I managed. Now the only problem I found is that the words ( SCORE<1> HIGH SCORE SCORE<2> ) are missing from the top of the screen. Thanks
  27. mkarlsson

    Changing the clock frequency

    No, the CMT can't do that. If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999). The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit. Hope this helps
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