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Logic Megawing SSEG display part number
flag26838 replied to flag26838's topic in Papilio General Discussion
Uhm, good question, probably only @Jack Gassett can help you here. - Yesterday
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I'd like to use a LogicStart Shield with a basic 5V Arduino UNO to use for early S/W design of a digital clock for a High School STEM program I am teaching. We need a 7-Seg display and some switches to set the time, timer, and mode of the clock. It looks like the slide switches would be fine but will the 7-Segment AN drivers be OK driven by 5V Arduino UNO outputs? As I recall, some of the individual LEDs have limiting resistors on the DUO so I'll stay away from driving those. Thanks, -Chris
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Hi Teaching Digital design and fpga we have enjoyed the easy integration with Xilinx ise. Now students find the webpack ise installation link leading to a VM installation. Is the non-VM installation still available ? What would be the preferred installation setup with the ISE in VM ?
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This question has already been asked but not for a very long time. Given the long time since the last discussion, I would hazard a guess that both have had major improvements. To which I ask which is the best out of the two? I will be using the board as an introduction to FPGAs as I have developed a keen interest in them as of late. As a theoretical physicist I never really encountered any electronics but an FPGA programmer at work gave me a CPLD to play around with after spending a few months of learning electronics. As such I already know a little about VHDL and could probably shift to Verilog without much fuss. The project I am thinking of doing first is to make the FPGA into a logic analyser for other project testing. tech news free netflix I know the Papilio has this feature as standard but given I want to make the project myself that doesn't really matter. What I want to know is, is the I/O routing on the Mojo good enough to allow the 100/200 MHz speeds the Papilio can reach? The Mojo is much easier to get hold of here in the UK whereas the Papilio would have to be imported. That being said the Papilio does have a bundle for everything to make it into a logic analyser (5V buffer boards and test clips) and I guess code which already works out of the box. PS: I would also appreciate any tips for getting a job in FPGA programming as a physicist given that the usual path would be for an electronics engineer. I am only a hobbyist yet but wouldn't mind having the option of my hobby becoming a career. I have already messed around with PICs and CPLDs with reasonable success.
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Logic Megawing SSEG display part number
keesj replied to flag26838's topic in Papilio General Discussion
Hi, Is it possible to control the COL-A and COL-C? The schematics for the Logic Megawing is not clear on this (and the ucf does not contain this information either) -
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Could you share your Verilog controller please?
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VERILOG SDRAM controller for Papilio Pro
Jose de Arimatea replied to Jose de Arimatea's topic in Papilio Pro
I'm writing a Verilog controller for this board. Does anyone want to help? I'm having some issues and it is not working yet: https://bit.ly/2GaBwRj -
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Introducing a new project - GadgetBox!
Tekna1 replied to Jack Gassett's topic in GadgetBox General Discussion
Interesting. -
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I recently was using my Papilio One and was erasing the spi flash using the papilio loader, when it disconnected and now it doesn’t show up when I try to upload a program. I tried reinstalling the drivers, but that didn’t work. I also installed the papilio loader on a different computer, and it as well didn’t see the board. The board, with the program that was already there, works fine, but I cannot upload anything new to it, since the computer can’t see the board.
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VERILOG SDRAM controller for Papilio Pro
Jaxartes replied to Jose de Arimatea's topic in Papilio Pro
Maybe. I don't know of one exactly. Here are some I do know of: Hamster (Mike Fields) wrote one that's been used on the Papilio Pro. But it's in VHDL not Verilog. And the links to his site aren't working tonight. Here's a thread discussing it: http://forum.gadgetfactory.net/topic/2551-hamsters-sdram_controller/. And here's one self contained project which used the controller: http://sowerbutts.com/socz80/. Here's an SDRAM controller written in Verilog, but it's for a different chip than the one used in the Papilio Pro: https://opencores.org/projects/sdram_16bit. I've got one, Verilog for Papilio Pro; but it didn't work. I gave up on it in April 2016. There are probably others, if you search. One that's in VHDL, not Verilog, might still be understandable enough to help you. One that's for a different SDRAM chip might still help you learn something. -
Logic Megawing SSEG display part number
flag26838 replied to flag26838's topic in Papilio General Discussion
Thanks, that appears to be the correct part number, now i just have to find it at a decent price... the 7ssegs on my logistart is toasted and i wanted to swap it. -
Logic Megawing SSEG display part number
bnusbick replied to flag26838's topic in Papilio General Discussion
Hi, I scanned the forum and saw the following thread: http://forum.gadgetfactory.net/topic/1439-ghosting-on-logicstarts-seven-segment-display/?tab=comments#comment-9086 which has a link to the following: https://www.sparkfun.com/datasheets/Components/LED/7-Segment/YSD-439AY2B-35.pdf which says Model No.: YSD-439AY2B-35. I can't guarantee this is the part number, but it has 8 leads on each side, which matches my logicstart megawing. -
What's the part number of the SSEG display employed in the logicstart megawing?
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Hi guys, I'm studying how to make my own SDRAM controller. I would like to study a Verilog controller for Papilio Pro to learn. Is there any Verilog SDRAM controller for Papilio Pro that I can check ? Thanks in advance!
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Just a quick comment that to generate a slower clock, a preferred method is to use a synchronous counter. This type of counter has all counter flops clocked by the same high speed input clock and fits well with the way that FPGAs handle clocks. It is also the way that this type of circuit would be designed in an ASIC. Here is some code I wrote recently (as an example). It divides 315MHz from a PLL to 3.57MHz. A divide by 88 is required. reg [6:0] pll315_counter; reg clk357; // create 3.57MHz NTSC clock by dividing 315MHz by 88 always @ (posedge w_clk315) begin clk357 <= (pll315_counter<7'd44); if (pll315_counter==7'd87) begin pll315_counter <= 7'b0; end else begin pll315_counter <= pll315_counter + 7'b1; end end You would need to change the counter length, termination count and half count to suit your frequencies. I should have really used constants (such as tick defines) rather than hard code numbers, but hey this is my personal hobby project 😃
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Hi James, Thanks for your reply. I re-positioned the picture by setting the VGA_Invert.vhd constant Horizontal & constant Vertical variables settings. Thanks for the website you recommended. I will try to understand something there.
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I'm afraid I can't be much help there, I never tried to invert the video, I've always just left it whichever way the original game was. Most arcade hardware has the ability to flip the screen for cocktail mode though so it should be a matter of just inverting whatever signal controls that in the game to flip the screen. Are you sure the monitor isn't just adjusted so that text is off the screen? I highly recommend reading Free Range VHDL http://freerangefactory.org/ It's free and was a big help to me when I was starting out. You will really need to learn VHDL (or Verilog) in order to get much out of your FPGA board, using only existing projects without being able to modify them is extremely limiting, once you know a bit of VHDL you can understand how they work and tweak things as needed.
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I asked around and realized that having the clock go through an inverted d flip flop divides the clock in half. I need 23 flip flops much like your 23-bit counter Thank You!
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James, thanks for replying. I don't think it's part of the project. As you may already know I am new to this FPGA thing. I downloaded it many times from GitHub and managed to make both Pacman and Space invaders work. The problem was that they are opposite to each other on the screen and you have to turn the monitor the other way round. Then I saw a thread on the forum named Video inversion for Invaders for space invaders by Marco. The problem was I could not create the u_invert file for it. But finally I managed. Now the only problem I found is that the words ( SCORE<1> HIGH SCORE SCORE<2> ) are missing from the top of the screen. Thanks
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No, the CMT can't do that. If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999). The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit. Hope this helps
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HELLO all, just started my papilio journey and I need to reduce the 32MHz internal clock down to just 5Hz. I tried reading materials about the CMT (clock management tile) but just got more confused. thank u Mar
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recapta V1 is shutdown when trying to create account
Henry Alonso replied to kvintus's topic in Gadget Factory
It has been fixed ! -
Right click in the project hierarchy, select New Source, then select IP Core Generator and from there you can create a memory. I'm not quite sure what you need that for though, is it not already part of the project? I'm pretty sure I have Space Invaders for both of the earlier Papilio boards somewhere, it's a project that I have ported to a number of different FPGA boards I have as sort of a "Hello World" type thing as it's known working code that is fairly simple to work with.
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Very well done both of you, I understand that Jack was upset about people buying knockoffs. But unfortunately I have bought both Original Papilio Pro & Mega wing from Jack, I guess! (Factory Gadget that is) I hope. My only reason I bought them is that I love arcade games which I got some help from James on a particular game. But later I needed some help on how to create a memory core to be called u_invert, to compliment the VGA_Invert.vhd for space invaders, and all I got is nothing even from Jack himself. Where is the support?I am still waiting. Thanks.
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Hallo all, I was very impressed seeing the linux kernel booting on ppro in your video, I downloaded the github repo with Linux3.7-zpu, but I have still big problems to get it compiled and I also couldn't find the source of zbflt-loader and zlinux-loader to get it running. Maybe someone has some useful tipps or a short tutorial. Thanks in advance
