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  2. Sbcglobal is one of the trusted domain names that is being used from the past decade, if you want to know more about sbcglobal.net email server settings then you are at the right place.
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  4. Chris Jones

    OLS update failure

    FWIW i've found several different utilities to manage the PIC firmware and the FPGA firmware for these devices. information is scattered about unfortunately. i've compiled a binary in the past using source provided by a github repo, and that can access the `APP` portion the board, which i believe is the FPGA portion, and can dump the contents in either HEX or bin, but have been unable to dump / backup the contents on the winbond chip using such provided utility. however my OBLS provided a means to solder a jumper header for SPI connection that allows me to connect jumper wires, thus i was able to use flashrom in conjunction with a bus pirate i have to dump the current contents of the winbond chip on the OBLS, i did not have to provide any power to the OBLS as the bus pirate can supply 3.3V to power the winbond chip to access its contents. i haven't tried to update or erase the contents of the chip using flashrom with a bus pirate, as i still need to figure out what versions i want to run and i'm still trying to gather all the necessary information for this device. i hope some of this helps.
  5. Gabriel K

    Where's Jack?

    I just bought a Papilio Pro from the Gadget Factory Store Website. I hope my order is fulfilled. ----- November 10 Until now my order was not fulfilled. I will update this thread regarding my purchase. ------ November 12 They shipped my order today! Someone is running the store. It is just a shame Jack has gone away. They could give us an update!
  6. Matt Ownby

    Powering Papilio One via 5V on 'wings'

    It is indeed 5V TTL. I am under the impression that I can just add 300 Ohm series resistors between the 5V outputs and the FPGA inputs (as discussed here: https://www.xilinx.com/support/answers/19146.html ). Is that not the case? The PROM is very simple: https://www.datasheetarchive.com/pdf/download.php?id=a8a991d4d97f7b8c9b56a785cdeb8f10562078&type=M&term=MB7052 It has 8 address lines, 2 enables lines, and 4 data outputs. So I am planning on adding ten 300 ohm series resistors for the address and enable lines. How does this sound? And yeah, I'd love to check out your project. I'd like to do more FPGA work in 5V TTL environments in the future.
  7. alvieboy

    Powering Papilio One via 5V on 'wings'

    I have done it successfully in the past, but make sure the jumper is indeed removed. Also ensure you use as much 5V and GND wing pins as possible to lower noise and increase current capability. However, I wonder if you are replacing a PROM which used 5V as IO voltage. In this case DO NOT connect it to the wings, since IOs on the FPGA are 3.3V. There are a few solutions to convert those signals, but will depend on the IO standard (TTL or CMOS) that your system uses. If it's a TTL system, then using some 5V-tolerant buffers should do the trick. I have a design which interfaces a 3.3V FPGA to a 5V TTL system, and seems to be working OK, I can send you a link for the project if you are interested. Alvie
  8. Hello, I want to use my Papilio One to prototype replacing an old PROM on an arcade PCB from the early 80's. The PROM gets 5V supplied to one of its pins. I was just looking at the Papilio One schematic in Eagle and it appears that I should be able to connect the 5V from the arcade PCB to one or more of the 5V outlets on the 'wings' as long as I completely remove the "PWR SELECT" jumper so that power is neither coming from the 5V regulator nor the USB port. Does this sound reasonable? (I apparently can't use the PWRIN connector since that seems to require 6V minimum, plus it's more convenient to use the wing anyway if I can)
  9. Asterion Daedalus

    OLS update failure

    I won't be much help, other to report I have repeated the problem with my v1.04 OBLS. Note, I did not place a jumper because the instruction appeared to suggest that was not necessary if both ACT and PWR led were on. However, I got the same errors. My Logic Sniffer ROM loader is v0.3 (November 9, 2010) as opposed to your Logic Sniffer ROM loader v0.4 (December 9, 2010). Cheers, A
  10. Hi, Can anyone suggest me suitable reference of serial communication with Papilio One board. I am unable to find any proper reference. Thanks
  11. papry

    Where's Jack?

    Hi Ben, yes the Papilio boards are a great choice. One of these boards was my very first FPGA board, and I have had lots of fun and frustration. Iniitially using the Papilio One didn't go well, but I managed to work through the various problems and finally was able to start writing my own code. Still no idea what has happened to jack :-(
  12. Ben Baker

    Where's Jack?

    I'm a new Papilio Pro user (bought one a few months ago from Seeed Studio) and have bought a few wings recently from the GadgetFactory store. I think the Papilio boards would still be great for beginners but unfortunately they're not for sale anymore. It's a shame so much work went into this product and it's seemingly abandoned. I also wonder what happened to Jack Gassett. I hope he's well!
  13. Benjamin Santiago

    Issue with OR and "floating" values?

    Hi I am currently working through Mike Fields'/hamsternz's pdf and have an encountered an issue. I'm up to the section about using buses (this is chapter 8). I do not have the Logic Start Megawing so I'm using LED's. I'm confident I hooked everything up correctly (I experienced something similar to what I will describe with the LED/button wing). So when I simply assign the switches to LEDs, or change the the assignments with the concatenation operator everything is fine. However, when I use only the OR operator, I sometimes get some of the LED's turning on in ways that are not correct and not predictable (ie when I let go, multiple LED's turn on). The final "problem" in chapter 8 is to take the 8 LEDs and 8 switches and make it such that the first 4 LED's show the result of OR-ing switches 0-3 with switches 4-7, and the other 4 LEDs show the result of AND-ing switches 0-3 with switches 4-7. AND behaves predictably but OR does not and I'm not really sure how to fix it. The closest I can get is to set the power line to 2.5V that just reduces the amount of "errors". I tried different resistors, different resistor values, switching around testing all switches and LEDs. I also tried to add the " | PULLDOWN" to the switches in the constraints file. Not sure what else I should do or if I'm missing something thanks! Ben
  14. theonlycasper

    (HELP) AVR Serial Port does not work.

    As for the AVR Serial Port, it still doesn't work. It's not used for separately programming the Papilio Duo's AVR chip as shown in the videos and learning material. It irks me that the official information is false and led me on a wild goose chase. I hope someone can shed some light as to why my Papilio DUO cannot program from the AVR serial port or the bootloader.
  15. theonlycasper

    (HELP) AVR Serial Port does not work.

    Figured out how this works with some help. I flashed the .bit file of my design to the internal ROM using Papilio Loader (SPI Flash), then used the FPGA to flash the microcontroller using ISP. After unplugging and replugging, both keep their memory and work with their respective designs. If you're using Xilinx ISE, set Arduino_Reset pin (P139) to high / '1' at the top level. If anyone is using avrdude, avrdude -p atmega32u4 -cstk500v1 -PCOM5 -b57600 -U flash:w:example.hex Make sure to directly load the FPGA with a Papilio_DUO_ArduinoISP.bit file, then flash the microcontroller. It won't overwrite the SPI Flash where the necessary .bit file is located and the Atmel chip has it's own separate memory as well. This AVR programmer will vanish after a power cycle. I hope this information can be helpful.
  16. theonlycasper

    (HELP) AVR Serial Port does not work.

    Please help. I have a Papilio Duo 512K and I am running Windows 10. I can't upload a sketch from the DesignLab IDE without the use of an ISP bit file. I need the FPGA for other needs, so I cannot program using ISP. I have read through and found that programming directly over USB is possible: http://learn.gadgetfactory.net/2015/01/15/designlab-quickstart-duo-avr/ However, this did not follow my expectations and the device is nowhere to be found. Every time I press the FPGA reset button, the Papilio DUO AVR Serial Port becomes available in device manager and DesignLab. The moment I upload or lift my finger off the reset button, the serial port vanishes into the hidden devices. Things I have attempted: Uploading while pressing reset. Burning the bootloader, but same issue as the AVR serial port. Multiple uninstalls and reinstalls of the DesignLab IDE (Version 1.0.8) and included drivers. FTDI driver installation. Unchecking Serial Enumeration. Direct connections to PC, No USB hubs. Please help me fix this issue.
  17. I have a question. I am new to this area. If the BRAM was not instanced. Can we still initialize it with data2mem? Seems that the BRAM is already instanced and already has an Instance Name. I have a already synthesized design and I want to write some additional information in a BRAM. In my understanding, the BRAM is always on the FPGA fabric. I just want to store a string in a BRAM. Thank you in advanced. Shixiang
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  19. RocketMan

    Wings vs Shield

    What's the difference between Logic Mega Wing vs Logic Shield?
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  23. Apologies as this is obviously somewhat off topic (different hardware). Previously I have compiled the VHDL source of the SUMP code for the Papilio One and successfully used it with the 5V level translater wings. This solution is incredible value, as even 8 or 16 bit logic "hobbiest" logic analysers cost many hundreds of dollars. Recently I bought a cheap FPGA board called the RV901T from China. I has 64 I/Os at 5V level (grouped into banks of 32). There are some direct FPGA connections too. However a stand alone Xilinx programmer is required and soldering skills to wire up the JTAG pins. The board has a Xilinx Spartan6 (like the Papilio Pro) but bigger (XC6SLX16). The original article was on Hackaday. So I started to write Verilog code to check that each pin toggled and that the direct FPGA pins could support serial comms using my own UART code. Good job I checked because I did need to remove a pull down resistor pack. Having got this far I decided to try to code my own logic analyser to be compatible with the OLD protocol and software. After a few bugs have been fixed from the LogicSniffer GUI I can get it to read the meta data. Question - can the device string be anything or for it to work does the software expect certain strings (device types)? Question - does anyone have a larger dump of all transactions over the serial comm port? Reason is I think the OLS protocol is not completely documented. Although the GUI sees the meta data it doesn't appear to ask for a capture. Perhaps it doesn't recognise my device "RV901T"? Any answers would be much appreciated. I intend to put the completed code on Github for others to use. BTW I was aware of the Pipistrello Verilog code which was helpfully posted in a earlier posting in this forum section. I have taken a look, but found the code hard to read.
  24. papry

    Where's Jack?

    Nice to see that all the spam postings have been removed/cleaned up. My question is the same, where is Jack Gassett?
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