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  1. Last week
  2. Hi, I've been developping some for some time a programm for the Papilio Duo 2MB (I didn't started this project, and the person who did left). So far, everything works well. If i'm not mistaken, the only part of the board using the SDRAM is the ZPUino (Vanilla v2.0). I have less than 20kB of code, so using a 2MB Papillio is a bit overkill. Therefore, when I wanted to make a second such board, I ordered the 512kB version that is cheaper. The problem is that now only part of the functionnalities work (I'm doing a kind of PID contoler : the input stage and one of the outputs works, but the second output (with lower bandwidth but better resolution) doesn't work, even if I plug it on the same external hardware). I suspect that I missed some parameter to change when switching between 2MB and 512KB. For the moment, the only thing I found to change was the type of board in DesignLab. However, I suppose that there is also something to change in ISE? Would one of you be so kind as to explain me what I have to change? Thanks a lot in advance Best felix PS : in addition to the ZPU, there are also some pieces of VHDL and schematics I did (but that don't use SDRAM) and a few pieces from libraries (I see no reason for them to use SRAM either)
  3. Hi, The code up until the last part looks quite similar to that I have done. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68 starts looking fishy. * Normally.. simply always use rising edges (and specially of the clock) * Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again.. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68
  4. Hi! I'm trying to create a library based on the "Wishbone VHDL" sample i think. I'm currently stuck trying to write to a wishbone register, the ZPUIno just locks up while the vhdl-module continues to happily tick without any noticeable changes. I've cross-referenced my code with the simple writeLeds example but I really can't see anything that should cause this lockup, please help!. ( btw I'm on an Papilio Pro board ) Here's my code:http://www.pcbindex.com/ I can see the print of line 13 just fine, line 14 initiates the write, and then it gets stuck and I never seems to reach line 15 https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/examples/simple_tremolo/simple_tremolo.ino#L15 which goes to: https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.cpp#L33 <- how i perform the actual register write https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.vhd#L98 <-- Here i try to receive/read. and finally.. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68 <-- unpack and act upon the command. but that never happens either, so i can only assume that something went wrong with the register write inside the zpuino and that the changes to the register were never applied.
  5. Path of least resistance for beginner..

    Could it be related to your USB chipset not recognizing that particular port for some reason? Did you rename/copy the dll's in your xilinx installation in win10? That was key for me. That and the ZPUIno image, and "MegaWing_Logicstart" sketch.
  6. Path of least resistance for beginner..

    Thanks again. I am starting to get the horrible feeling my Papilio One has developed a fault in the 2-3 years it's been in storage (in an anti-static bag). I fired up a Windows 7 VM in VMWare Player, I can upload the sample .bit file to the flash memory but when I connect to COM1 I get nothing. I will try a few other files and see.
  7. Path of least resistance for beginner..

    Hm. Can't remember what I did specifically, but I think I used usbview.exe Looking further, I remember I had to replace something in the xilinx installation folders too, if memory serves: https://www.xilinx.com/support/answers/62380.html Something about replacing one dll with another file from the installation in a couple of spots. Definitely something along those lines. Cheers, Rob
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  10. Path of least resistance for beginner..

    Thanks for your response. I am getting no serial port available and getting USB timeout issues when trying to transfer a .bit file. I have tried the tip of deleting the Papilio drivers and using the W10 ones, but not getting any further.
  11. Path of least resistance for beginner..

    Which part are you stuck on? I vaguely recall some 3rd party USB utilities I used in this process.
  12. Path of least resistance for beginner..

    Be interested to know how you got around those Windows 10 issues. It is fighting me every step of the way!
  13. Earlier
  14. New (potential) user

    Hello all, thinking of picking up the Duo with a LogicStart shield. I'd like to possibly integrate with my Arduino classes at the HS level in conjunction with FIRST robotics - Our current learning platform is Arduino Uno based. I have a EE background with embedded programming experience but minimal FPGA design experience. I've read thru much of the VHDL intro (e.g. Freerange VHDL) and it seems fairly intuitive. Questions: Are there any issues with Windows 10 and any of the EDAs for this or other Gadgetfactory boards/FPGAs? Any idea when the larger boards (e.g. 2M Duo) will be available? Any other advice? Many thanks, -Chris
  15. wishbone address bits

    Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on. https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251
  16. wishbone address bits

    I would guess the reason for the "downto 2" is that the bus address is in word (32 bit) units while the addresses seen by code are in byte (8 bit) units. Thus, with "26 downto 2", the numbers of the bits more closely correspond with the processor address space, i.e. wb_adr_i(10) will be byte 1024 (2**10). At least that's why I did the equivalent in my own 32 bit design.
  17. I found the answer myself : In the IDE : File -> Upload using programmer Or use the Papilio_DUO_ArduinoISP.bit to turn the FPGA into a programmer, and interface with avrdude # papilio-prog -f <path to bit file>/Papilio_DUO_ArduinoISP.bit # avrdude -C <path to avrdude config>/avrdude.conf -v -patmega32u4 -cstk500v1 -P/dev/ttyUSB1 -b57600 <Other arguments> WARNING: please make sure what you are doing, if you change the fuse bits to the wrong settings, it can make your atmega32u4 totally useless, and the chip will have to be replaced.
  18. Hi, I'm working on a project to get a C64 emulator running on the Papilio DUO. I have a working setup using uno2iec program to emulate the disk drive, but this still requires a laptop connected to the board. I found a project named sd2iec, that uses the SD card to load disk images of, but the compiled program is too big to fit on the ATMega32U4 together with a bootloader. So I need a way to program the AVR directly. I Googled for documentation on how to use the bootloader program routine to upload my software as well, but couldn't find any. Is there a way to program the AVR on the Papilio DUO without bootloader via USB using for example avrdude? Kind regards, Paul
  19. Papilio DUO Gameduino sketches not compiling

    Hi, sorry for the late reply I did get it to work in the end. Selecting the AVR board instead of the FPGA did make a difference, since the source won't compile for the soft cpu.
  20. wishbone address bits

    Having talked with a few people about this I think the code would better be rewritten as signal wb_adr_i: std_logic_vector(23 downto 0); then case wb_adr_i(0) becomes the first bit It is possible that the bits 23 downto 19 or contain the wishbone address?
  21. Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ?
  22. Hello guys, I would like to make a hardware cosimulation with a circuit made in System Generator. Does anyone know how to complete this windows in order to add a new compilation target (Papilio Pro)? Thanks in advance!
  23. Wishbone_to_Registers lisence

    No, consider that code public domain code. Feel free to do whatever you like with it. Jack.
  24. Hi, I have a working screenbuffer at 50Hz, so I decided to send a bit file that contains a working version of the fpga64 emulator. The zip file includes a readme to explain how to get the C64 diskdrive emulation working. Kind regards, Paul Honig fpga64_papilioduo.zip
  25. Hello,I am working on a modified version of Wishbone_to_Registers does including it in my project mean anything about the license of my own code?
  26. Papilio loader: Null-pointer

    Hello. I just wanted to note that this is still an issue, and not easily googleable. It'd be nice if a fix could be implemented I had to help a friend get the loader to run again. Friend is running: Latest windows 10 ISE 14.7 webpack for windows 7, with dll fix to work on windows 10. We opened CMD, entered the directory of papilio loader, ran: java -jar papilio-loader.jar "programmer/bscan_spi_xc6slx9.bit" This opened papilio loader as it should. Then we opened preferences, and unchecked the "load last bitfile" option, and now it works as expected.
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