All Activity
This stream auto-updates
- Last week
-
I just purchased the Duo 2MB + LogicStart Shield Combo. Two questions: 1. Which wings and megawings (if any) can I use with the Duo? 2. When (if ever) do you expect the Computing Shield to be back in stock?
-
mdavidjohnson joined the community
-
Rajiv Tyagi changed their profile photo
-
pumainterior joined the community
-
Parash changed their profile photo
-
patiknot changed their profile photo
- Earlier
-
I am also experiencing problem in writing SPI flash of Papilio Pro now, nevertheless it was all OK until April 10, a week ago. Writing to FPGA is still working correctly. The full log output on Papilio Loader 2.8 (on Windows 7) is: -- JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "C:\Program Files\Gadget Factory\Papilio Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0x79c7e6969e763cff Done. Programming time 1051.1 ms Programming External Flash Memory with "C:\FPGA\TimingMeas1\timingmeas1.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ......Ok Verifying : ...Error in Verify: first byte of data [0x00] .. Failed (@ Page: 515) Using devlist.txt Error occured. USB transactions: Write 709 read 541 retries 0 JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt ISC_Done = 1 ISC_Enabled = 0 House Cleaning = 1 DONE = 1 -- The strange points of those errors are that the page numbers of the error positions are changing every time, like: [ The 1st time ]: Failed (@ Page: 515) [ The 2nd time ]: Failed (@ Page: 936) [ The 3rd time ]: Failed (@ Page: 257) I hope those errors are not due to broken hardware. ======== [p.s. (April 22)] As far as I found having retried in various ways, it seems Windows 7/10 update around April 10-14 made bad effects on USB communication, since the log output on Papilio Loader was rarely like: -- Programming External Flash Memory with "C:\Users\Desktop\timingmeas1.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ....Error: SPI Write Check Status Register [0xFF] mismatch (Wrong device or device not ready).. ..Ok Verifying : Using devlist.txt .Error in Verify: first byte of data [0x00] .. Failed (@ Page: 39) Error occured. USB transactions: Write 234 read 66 retries 0 JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt ISC_Done = 1 ISC_Enabled = 0 House Cleaning = 1 DONE = 1 -- ..., showing the error was caused in "Partial Erase" phase, meaning USB communication errors are happening everywhere. This USB communication bug might be affected by Windows update, and can be found in an other person's tweet on Apr 14 (in Japanese), ..., meaning there are some strange points in FTDI VCP communication. My two Papilio Pro boards became unavailable with Papilio Loader now. I am wondering if I could use other JTAG tools to write flash without damaging the Papilio Pro boards.
-
Hey All, I'm wondering if there's any plans for future development of the Papilio range of boards? I'm a big fan of Papilio Duo with the Classic Computing Shield - it's got everything I need for my typical projects which is primarily old retro machine emulation. Recently however I've become interested in playing around with some of the newer Xilinx chips (and perhaps the Intel/Altera FPGA's) but I'm having a hard time finding development boards like the Papilio with everything baked in: onboard RAM, SD card, VGA (or HDMI) output, audio output, PS2 etc... I guess this post is just wishful thinking, but curious if there's anything in the pipeline. Brad
-
domiosports joined the community
-
DOVYDAS changed their profile photo
-
rcon303 changed their profile photo
-
As my first project using the Papilio Pro and LogicStart MegaWing, I made LEDs turn on from the switches. When I use the Papilio Loader 2.8 to write to FPGA, it executes fine and I am able to turn on the LEDs. When I try to write to SPI Flash, however, it times out and displays the following error message: readusb: Timeout readusb terminate called after throwing an instance of 'io_exception' What am I doing wrong? Full Output: JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "C:\Program Files (x86)\Gadget Factory\Papilio Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0x39bd53c11674cfff Done. Programming time 698.6 ms Programming External Flash Memory with "C:\Users\Jay\Desktop\ISE_Projects\Switches_LEDS\Switches_LEDS.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ......Ok Verifying : ......Pass Programming : ......Ok Verifying : Using devlist.txt ......Pass Done. SPI execution time 17465.5 ms USB transactions: Write 6853 read 6684 retries 0 Using devlist.txt readusb: Timeout readusb terminate called after throwing an instance of 'io_exception'
-
Vector22 joined the community
-
naveen joined the community
-
taimurr joined the community
-
Elbeji Mourad changed their profile photo
-
Logicstart Shield compatibility with 5 V Arduino UNO
F6EEQ replied to Chris Wilcox's topic in Papilio Wings
Funny enough, but the LED's have 330 ohms limiting resistors, but not the 7 segment., at least this is what I see on the Megawing schematic.. I checked the 7 segment notice, so it is said 20 mA, and 2.1 V typical, but nothing about a limiting resistor, which is always good to have in my opinion. I don't know why Jack did not provide these... Anyway, when I use a LED (anyone) with an ARDUINO, it is always safe to have a limiting resistor (330 ohms if you wish a bright glow, but 1 k should do the trick). More important: ARDUINO provides 3.3 or 5 V, so be sure not to overload the Megawing! Have fun. Gerard. -
Hi all, I have 2 question about 7 segments on Logic start Megawing: First: some segments are always "on", even if I do not use them (not always the same). I suppose that the FPGA pins are in some "random" state and that this could give some lighted segments. Also to light the segments, the anodes must be in a "high" state. I could switch them off in the code, but this is not a very elegant solution. Is it possible (for instance in the UCF file) to declare these pins as logical zero, or to say that the anodes (AN0...AN3) are to ground, so as to block the +3.3V supply? Second: in the schematics, the decimal points are on the bus and appear on the pins. But the colon and Apos are on the bus but do not appear on pins. Is there a possibility to light them? Thanks a lot for your help. Gerard.
-
Hello everyone,, I got my Papilio DUO the other day and have been playing around with. Let me say I really like what I see. I only had a couple issues(drivers but got fixed), less than most development boards I have used. My main project for buying the DUO was for 3d printing. As I mentioned in an my intro post I think the DUO is a great platform for this. I have started working on splitting up the Teacup firmware for arduino. I put together a small document with my ideas on how a 3d printing firmware might work on the DUO. Looking for others thoughts especially on the FPGA side of things as I am just starting out learning that side. Feel free to chime in on any thoughts. I broke it down into 2 phases just to make the coding a little easier on my end. The 1st phase is just moving all the motion planning and control over to the ZPUino. The later phase will be the better stuff, moving the stepper control out of the ZPUino and just plain fpga, but leaving the motion planning on the ZPUino.youporn.wiki/ xhamster.vip/ redtube.onl/ One of the areas I am especially looking for some input is how to bridge the atmega32U4 to the ZPUino. I need to send data (positions for each axis, estop, etc) to the ZPUino and possibly request data in return (current position) from also. My first thought is something like SPI or I2C over some of the shared pins. I would love to hear if there are some easier or faster or more efficient approaches. Another item I am looking for some feedback is in the Phase 2 area. I showed two possible configuration for how I think it might be done. Any feedback on those would be appreciated also.
-
Hello everyone,, I recieved my LogicStart today so as I have a few hours spare I thought I'd get cracking wth Hamster's PDF of tutorials and info. I've just finished making a 4 bit adder using the swithces and LEDs of the board and would like to know if my code looks right. It seems to work.. From right to left, the switches in 2 groups of 4 seem to add up all the way to 15. The code is here: xvideos.onl/ xnxx.onl/ chaturbate.onl/ entity switches_leds is Port ( switches : in STD_LOGIC_VECTOR(7 downto 0);LEDs : out STD_LOGIC_VECTOR(7 downto 0));end switches_leds;architecture Behavioral of switches_leds issignal x : STD_LOGIC_VECTOR (3 downto 0);signal y : STD_LOGIC_VECTOR (3 downto 0);signal carry : STD_LOGIC_VECTOR (3 downto 0);signal result : STD_LOGIC_VECTOR (4 downto 0);beginLEDs <= "000" & result;x <= switches (3 downto 0);y <= switches ( 7 downto 4 );result(0) <= x(0) XOR y(0);carry(0) <= x(0) AND y(0);result(1) <= x(1) XOR y(1) XOR carry(0);carry(1) <= (x(1) AND y(1)) OR (carry(0) AND x(1)) OR (carry(0) AND y(1));result(2) <= x(2) XOR y(2) XOR carry(1);carry(2) <= (x(2) AND y(2)) OR (carry(
-
Hi Magnus, I had some issues with some codes, but looking through other codes, I noticed the problem. I don't remember why using posedge on a button was a good idea in my head. Anyways, thanks a lot. I have fixed the issue the tuesday afternoon. Oskar
-
Here is the problem - you take the signal from the button connected to pin C4 and use that as a clock for the ledst0 flip-flop. This is not how you use an FPGA. Pin C4 is not a clock input pin, which cause the error 1108 you see, and logic signals like btnl should not be used as a clock. FPGAs are intended to be used for synchronous logic designs where a large number of flip-flops are clocked with a common clock. In order to make this possible the clock is distributed to all the flip-flops in this clock domain using special clock buffers and clock networks. The source of the clock is typically coming from an input pin on the FPGA and only a select few pins can be used as clock input. The input clock can be used as is or can be feed to a clock management tile that has resources like PLLs and DCMs that allow you to create a clock with different clock frequency. The Nexys3 board has a 100 MHz clock input signal connected to pin V10 that can be used as system clock. This is what the Nexys3 manual states: Try this code instead: .ucf file: BTW, your switch might "bounce", so you might have to de-bounce the signal from the switch. See What is debouncing? Magnus
-
Hello everyone,, I was wondering if anyone had any input, pro or con, on the Papilio FPGA dev boards. They look like good learning tools, with a decent hobbyist community. My goals: Learn the basics mobdro lucky patcher kodi about FPGAs - I'm starting from scratch (experience with PIC16/18 and ARM9, basic electronics, PC programming). Primary application: FPGA based ADS-B receiver/decoder. Other applications: DSP of other RF signals, maybe playing with graphics generation.
-
Hello everyone,, This question has already been asked but not for a very long time. Given the long time since the last discussion, I would hazard a guess that both have had major improvements. To which I ask which is the best out of the two? I will be using the board as an introduction to FPGAs as I have developed a keen interest in them as of late. As a theoretical physicist I never really encountered any electronics but an FPGA programmer at work gave me a CPLD to play around with after spending a few months of learning electronics. As such I already know a little about VHDL and could probably shift to Verilog without much fuss. The project I showbox.bio/ tutuapp.uno/ vidmate.vet/ am thinking of doing first is to make the FPGA into a logic analyser for other project testing. I know the Papilio has this feature as standard but given I want to make the project myself that doesn't really matter. What I want to know is, is the I/O routing on the Mojo good enough to allow the 100/200 MHz speeds the Papilio can reach? The Mojo is much easier to get hold of here in the UK whereas the Papilio would have to be imported. That being said the Papilio does have a bundle for everything to make it into a logic analyser (5V buffer boards and test clips) and I guess code which already works out of the box. PS: I would also appreciate any tips for getting a job in FPGA programming as a physicist given that the usual path would be for an electronics engineer. I am only a hobbyist yet but wouldn't mind having the option of my hobby becoming a career. I have already messed around with PICs and CPLDs with reasonable success.
-
Nigan joined the community
-
RDANVILL changed their profile photo
-
Seems nice, but I've been unable to open the link.... Which soft could open it?? Thanks Gerard.
-
Great, than you ... We did lots of new stuff with FPGArduino, and recently we developed new version of our FPGA board that is supported by new opensource tools http://radiona.org/ulx3s/ you can check few tutorials/presentation/samples here: https://github.com/ulx3s/fpga-odysseus/blob/master/presentation/FPGA Odysseus.pdf
-
FPGArduino - where FPGA meets Arduino - FER
vhdlspain replied to mistery's topic in FPGA Discussions
Hello, Talking about FPGA and Arduino, here you can find a tutorial about connecting a FPGA to Arduino using I2C. https://vhdl.es/arduino-fpga/ -
vhdlspain joined the community
-
xrvak changed their profile photo
-
Hi, I'm back on Papilio and I would like ti interface with a LCD to be able to follow what is going on. Easy to do with PIC or ARDUINO, but not so much with FPGA. I browsed the web (FPGA4fun for instance or Hamsterworks) but did not find any usable tutorial. I do not wish to go with ZPuino or the like, but pure FPGA things. Playground did not provide any help on this matter either, although there is a LCD on the retro wing. Could some one help me? I'm not looking for a ready-to-go project ( butit could help) but rather some educated hints on how to proceed. Thanks in advance. Gerard.
-
Hi, I´m making a emulatorfor an FPGA Spartan6 XC6SLX16-CSG324C (Its a Nexys 3 board). When I tried make something more complex than light an LED, I though the problem was mine. But, I tried make a simple program to know the issue. This program, a simple botton-led, I use the C4 pin and U16 pin. The problem is the C4, a button, does the next error. Alright, some good being, told me to use the solution of: 1- Change the button to other that works (Works fine, but... there only works 3 buttons from 6, and one is the RESET button) 2- Use the "NET "btnl" CLOCK_DEDICATED_ROUTE = FALSE;", this, doesn´t work fine in the board. I looking for any new solution that might work. I also have the original proyect that don´t have any of this issues, but it´s a bit strange. The code is the next: And the .ucf file: Any help would be apreciated.
-
Oskar STEPIEÑ joined the community
-
tktktk changed their profile photo
-
Hello together, On my Duo Board I am using the Softcore on the FPGA as my Microcontroller. In the Design Lab there are several libaries available, also the SPI libarie. I need the DUO Board to work as a slave but in the libaries nothing like this seems to be implemented. Did someone already do this and can show me how it is done?
-
delfare changed their profile photo
-
Hello. I'm just starting to learn ISE with the Papilio Duo. My first step was to create a circuit to read & write 1 bit from the onboard SRAM. However, I've hit a wall that I can't understand how to work around and was hoping someome could helpme figure it out. Here is the circuit I have thus far (attached) - basically connected an 8bit IBUF and OBUF to the sram data lines and just all 0 to the address lines. However, it won't synthesize: It gives this error: ERROR:Xst:1850 - Unable to insert IOBUF on port <sram_data<0>> in unit <SRAMOutput> having KEEP_HIERARCHY constraint. There are feedbacks in other units. Searching the Xst forums suggests turning off the KEEP_HEIRARCHY constraint, but it is already off in the settings and I don't understand why it is an issue since I have no other components / levels. Any ideas greatly appreciated. Thanks.
-
Hi all, just wanted to share this with the whole community: https://www.hackster.io/salvador-canas/a-practical-introduction-to-sdr-sdram-memories-using-an-fpga-8f5949 regards
-
Could not load into board for both xilinx and zap
Ricky Yuu replied to Ricky Yuu's topic in Papilio One
Its okay I have found the solution, the USB itself holds an important role. Now, I want to test out where to upload for the ZAP IDE. I will update the progress here. Thank you. -
Hey, LambdaPi I have found the solution with the issue perhaps you should using the USB power jack that has cylindrical around the USB. I hope it will help you a little bit
-
I also have similar problem.
-
Hi, As the link of the video below, i have followed each steps as on the final steps on loading the ZAP i could not upload it, as first what is the board it is used as there's variety of papilio one 500k ( how can i differentiate it?) and the port of the COM of the ZAP IDE does not show up. i could not upload into the board has been installed and un-installed papilio loader and ZAP IDE. I could not find the solution and been running this for two weeks. I am using papilo one 500k. Currently my papilio loader could not open. Could you please pointed out my mistakes in this case, such as if i don't download any necessary software beside Xilinx ISE, ZAP IDE and papilio loader. I am current;y using window 7 for this project. (https://www.youtube.com/watch?v=E1PkdcALyz8&t=132s) thank you very much. Ricky
-
Hi, I downloaded the latest version of DesignLab (version 1.0.8) but my AV (Avast) reports it as containing FileRepMalware. I'm pretty sure this is a false positive but can anyone confirm either way? Thanks.
