I've built the Z80 CP/M variant, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this:
1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, Z80, VGA, Serial, Keyboard, SD-Card) from the original design to fully use the Computing Shield peripherals and the DUO's SRAM (using and updated Computing Shield UCF file).
2. Converted the original 6 bit color VGA to 12 bit color interface.
2. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx's Core Generator's Block Memory instead of the original Altera Altsyncram IP.
3. Converted the internal double port Display & Attribute RAMs also to use the Core Generator's Block Memory instead of the original Altera Altsyncram IP.
4. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio's 32 MHz OSC instead of the original 50 MHz, but I ran into timing problems converting the many clock -dependant constants in the design. So I decided to generate a new 50 MHz clock using the DCM & PLL Wizard.
Wherever possible I tried to maintain Grant's original VHDL & Z80 code, generating new signals and "wrapper" code to adapt to the different hardware. This way you can still refer to the original design as a rich learning experience, as every source code is available and well explained in Grant's website.
The final outcome is a very usable and complete Z80 soft-core based machine, running the venerable Digital Research CP/M 2.2 OS. The modular design concept allows for extensive hacks and mods, even CP/M 3 and MP/M could be run (my next milestrone !).
Hope you enjoy it ! I've attached some pictures of my working system and the full VHDL ISE 14.7 Project tree files, including an already generated "bit" file for transferring it to the Papilio Duo with the Computing Shield attached (default serial port baudrate is 9600, 8N1 no handshake).