Sign in to follow this  

"Sump" Logic Analyzer


Dhia
  • The "Sump" Logic Analyzer supports 32 channels with 6K sample memory or 8 channels with 24K and runs up to 200MHz. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. This project is synthesized for the Papilio One and shares the same code base as the Openbench Logic Sniffer project.

Features

  • 6K sample memory at 32 channels, 24K sample memory at 8 channels
  • 32 channels sampling at 100MHz
  • 16 channels sampling at 200MHz
  • Four stage serial and parallel triggering
  • External clock input
  • Noise filter
  • RLE built into the hardware to make the most of available memory.
  • SPI protocol analysis (SPI debugger)
  • I2C protocol analysis (I2C debugger)
  • UART protocol analysis (UART debugger)
  • State Analysis

Limitations

  • The FPGA can only sample 1.2V, 2.5V, and 3.3V. Any higher voltages can damage the input pins of the FPGA. Given time a plugin board will be developed to address this issue.

NOTE: The current 2.12 release is based on the Openbench Logic Sniffer 2.12 source code. There are issues with RLE, test mode, and there are some failing timing constraints in the project. This release has not been well tested, it is being released while the new Verilog branch of the project is completed. The Verilog branch should fix all of the above issues and will be available soon.

Sources and Attribution

  • Michael Poppitz was the original author of this great Logic Analyzer design. He wrote the original VHDL and Java client and released it GPL at http://www.sump.org/projects/analyzer/. Please visit his website for more information.
  • Jonas Diemer took the original design and ported it to the Spartan 3E by utilizing BRAM instead of SRAM he also integrated a RLE into the design. His source can be downloaded here.
  • The very latest development for the Java client is hosted on SourceForge here.
  • OakMicros has created a very nice tutorial for the Java client here . They also offer a nice buffer card to allow any Voltage level to be sampled. It is not currently compatible with the Butterfly Platform but watch for an adapter in the future.

Screenshots

main_window_scope.png

Main window (light theme) with scope.

main_window_tooltip.png

Main window (light theme) with measure tooltip.

main_window.pngMain window (dark theme).

measure_tool.pngMeasurement tool.

ols_config_general.png

OLS general settings.

ols_config_triggers.pngOLS trigger settings.

preferences.png

General preferences.

For More informations about this project please visit the Sump Logic Analyzer wiki page


Download Source Code
  Report Article
Sign in to follow this  


User Feedback


There are no comments to display.



Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now