- 6K sample memory at 32 channels, 24K sample memory at 8 channels
- 32 channels sampling at 100MHz
- 16 channels sampling at 200MHz
- Four stage serial and parallel triggering
- External clock input
- Noise filter
- RLE built into the hardware to make the most of available memory.
- SPI protocol analysis (SPI debugger)
- I2C protocol analysis (I2C debugger)
- UART protocol analysis (UART debugger)
- State Analysis
- The FPGA can only sample 1.2V, 2.5V, and 3.3V. Any higher voltages can damage the input pins of the FPGA. Given time a plugin board will be developed to address this issue.
NOTE: The current 2.12 release is based on the Openbench Logic Sniffer 2.12 source code. There are issues with RLE, test mode, and there are some failing timing constraints in the project. This release has not been well tested, it is being released while the new Verilog branch of the project is completed. The Verilog branch should fix all of the above issues and will be available soon.
Sources and Attribution
- Michael Poppitz was the original author of this great Logic Analyzer design. He wrote the original VHDL and Java client and released it GPL at http://www.sump.org/projects/analyzer/. Please visit his website for more information.
- Jonas Diemer took the original design and ported it to the Spartan 3E by utilizing BRAM instead of SRAM he also integrated a RLE into the design. His source can be downloaded here.
- The very latest development for the Java client is hosted on SourceForge here.
- OakMicros has created a very nice tutorial for the Java client here . They also offer a nice buffer card to allow any Voltage level to be sampled. It is not currently compatible with the Butterfly Platform but watch for an adapter in the future.
Main window (light theme) with scope.
Main window (light theme) with measure tooltip.
OLS general settings.
OLS trigger settings.
For More informations about this project please visit the Sump Logic Analyzer wiki page
Download Source Code