The Papilio Arcade Kit is a DIY kit thatprovides everything needed to recreateclassic Arcade games such as Pac-Man.Open Source HDL projects provide thehardware definition for study,implementation, and extending.The Papilio Arcade Wing provides, 12bitVGA, Delta-Sigma Audio, and DB9 Joystickports.
ZPUino is an implementation of the 32-bit Open Source ZPU processor. It is a small implementation that is meant to be used with the Arduino IDE. It is capable of speeds up to 100Mhz and can run on the Papilio Platform.
I can't get this to work, all i get is "Digilent Plugin: no JTAG device was found.", on plugin version 2.4.4 or 2.5.2
I'm using a generic ft2232h breakout that i've set to use the FTDI vid/pid (and even tried setting the correct manuf/description as well as user area contents, no change).
It's supposed to show up as USB Serial Converter A and B, right ?
max_counter has an initial value of all 1's but never assigned any other value so it's basically a constant. The warning is just another way of saying that.
As for the timing of this block, I'm not sure what you are trying to accomplish here. A 20 bit PWM circuit clocked at 200 MHz will have a period of about 200 Hz so you will need a very low frequency low-pass filter (~50 Hz) on the PWM output if you are trying to implement some sort of DAC. In general, for PWM DACs and delta-sigma DACs, the more bits of resolution you have the lower frequency components will show up on the output. Maybe your application is fine with a 50 Hz cut-off on the output, if not then I suggest rethinking your design.
I'm not sure this relates to your project but this thread might have useful information: http://forum.gadgetfactory.net/index.php?/topic/2378-cd-quality-audio-441khz-delta-sigma-dac-spartan-6/
I need help tracing down a warning and general improvements.
Here is the warning:
Signal <max_counter> is used but never assigned. This sourceless signal will be automatically connected to value 11111111111111111111
Here the VHDL code for a 20-bit PWM:
entity Generic_PWM_x1 is
clk: in std_logic;
pwm_var: in std_logic_vector(19 downto 0);
pwm_out: out std_logic
architecture Behavioral of Generic_PWM_x1 is
signal counter: std_logic_vector(19 downto 0):= (others=>'0');
signal max_counter: std_logic_vector(19 downto 0):= (others=>'1');
if rising_edge(clk) then
counter <= std_logic_vector( unsigned(counter) + 1 );
if counter=max_counter then
if counter<pwm_var then
It seems to me that it's assigned, so I need some guidance. In general, I'm also interested in improving the timing of this block, so any suggestions would be very much appreciated.
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