The Papilio Arcade Kit is a DIY kit thatprovides everything needed to recreateclassic Arcade games such as Pac-Man.Open Source HDL projects provide thehardware definition for study,implementation, and extending.The Papilio Arcade Wing provides, 12bitVGA, Delta-Sigma Audio, and DB9 Joystickports.
ZPUino is an implementation of the 32-bit Open Source ZPU processor. It is a small implementation that is meant to be used with the Arduino IDE. It is capable of speeds up to 100Mhz and can run on the Papilio Platform.
I have the same problem using Ubuntu with ISE 14.7 and a Papilio DUO.
For example, when I create a blank project in DesignLab, edit the circuit with ISE and then generate a bit file, ISE creates a file called "Papilio_DUO_LX9.bit". However, when I try to load the file with DesignLab, it looks for and loads "papilio_duo_lx9.bit" (lower case), which is the original blank project.
Here's what I think is going on, based on looking at the code in https://github.com/jamesbowman/swapforth/tree/master/j1b/verilog. I think it indicates a read from some I/O device's registers. That is, instead of reading/writing memory, the instruction reads some data provided by one of the peripheral devices.
This is one of the common ways a computer design could allow access to I/O devices. It looks like J1B uses a mixture of port-mapped and memory-mapped I/O (see https://en.wikipedia.org/wiki/Memory-mapped_I/O): as I look in xilinx-top.v I see that some memory accesses go to registers such as "uart_baud" too.
Analysis in more detail:
In j1.v: When "insn[6:4] == 5" then func_ior is asserted to 1.
When that is true (along with some other things) then the output signal "io_rd" is asserted to 1.
In xilinx-top.v: The signal io_rd is delayed one clock cycle (as io_rd_) and used, along with mem_addr (delayed as mem_addr_), to receive from the UART (see the signal uart_rd).
Thanks! I stuck with it and found the "clocking wizard" and saw how it had added the module to the symbol list for my project. One problem during simulation it complained during build about not being able to find the ports. I had named them in upper case in the wizard (CLK_IN1, CLK_OUT1), After checking the forum I tried naming them in lower case in the wizard and the project compiled and ran without trouble after that.
As for the clock input, I downloaded the Eagle files and traced P94 (OSC_IN) to the output of the 32MHZ oscillator chip - realizing that should be the pin I map to the CLK_IN on my circuit in the user constraints file (.ucf)
The CMT (Clock Management Tile) is a block containing one PLL unit and two DCM units. You can either instantiate a PLL or DCM unit directly in your code or use the "clocking wizard" to do it for you. The clocking wizard is part of the Xilinx CORE generator (under FPGA Features and Design -> Clocking -> Clocking Wizard). To learn more about the CMT, PLL and DCM check out this document: Spartan-6 FPGA Clocking Recources User Guide
This guide will tell you how to directly instantiate a PLL or DCM unit (or any other library component) in your code: Xilinx Spartan-6 Libraries Guide for HDL Designs (page 99 and 213 for DCM and PLL).
You should use the 32 MHz on-board oscillator as your clocking source, not the AVR SPI clock.
If you let us know more about what you want to do (like I want to generate a 100 MHz clock for my circuit, how do I do that?) then we can give you more specific help.
Edit: BTW, if you just want a clock input to your design but don't really care about the frequency then just use the 32 MHz on-board oscillator as your clock source, no need for a PLL or DCM. You only need a PLL or DCM if you want to generated a different clock frequency (or multiple clocks with different clock frequencies). For example, if your circuit has a VGA controller that needs to be clocked at 25 MHz then a DCM or a PLL will let you generate that clock from the 32 MHz input clock.
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