Forums

  1. Papilio Platform

    1. Papilio General Discussion

      For topics that apply to both the Papilio One and the Papilio Pro!

      819
      posts
    2. Papilio Pro

      New Papilio Board that adds a Spartan 6 and SDRAM to the Papilio One footprint.

      1,686
      posts
    3. Papilio One

      Discussions about Papilio One Gadget Board.

      1,594
      posts
    4. Papilio DUO

      FPGA and Arduino together at last!

      1,318
      posts
    5. Papilio Wings

      Papilio Wings are Open Source peripherals that snap into the Papilio for easy extendability.

      483
      posts
    6. DesignLab IDE

      DesignLab IDE lets you draw FPGA circuits without learning VHDL/Verilog. (Formerly ZAP IDE)

      621
      posts
    7. DesignLab Libraries

      Talk about libraries for DesignLab. Whether you are making them or using them, this is the place to discuss or request new libraries.

      259
      posts
    8. RetroCade Synth

      Chiptune synthesizer with C64 SID, YM2149, and POKEY audio chips.

      714
      posts
    9. Papilio Arcade

      The Papilio Arcade Kit is a DIY kit thatprovides everything needed to recreateclassic Arcade games such as Pac-Man.Open Source HDL projects provide thehardware definition for study,implementation, and extending.The Papilio Arcade Wing provides, 12bitVGA, Delta-Sigma Audio, and DB9 Joystickports.

      573
      posts
    10. Papilio Loader Application

      The Papilio Loader Application collects all of the functionality of the Papilio One into one installable application.This is still a work in progress.

      382
      posts
    11. Papilio Logic Sniffer

      Discussions about using the "Sump" Logic Analyzer with the Papilio Boards

      55
      posts
    12. 169
      posts
  2. Electronics

    1. Modules

      Electronic Modules that can be used with the Papilio.

      33
      posts
  3. Soft Processors

    1. ZPUino

      ZPUino is an implementation of the 32-bit Open Source ZPU processor. It is a small implementation that is meant to be used with the Arduino IDE. It is capable of speeds up to 100Mhz and can run on the Papilio Platform.

      498
      posts
    2. J1 Forth

      Discussion about the awesome J1 Forth Processor made by James Bowman.

      29
      posts
    3. AVR8 Soft Processor

      The AVR8 Soft Processor is an Open Source RISC processor that implements all the registers and instructions of an ATmega103 processor. It supports the avr-gcc toolchain for compilation of ANSI C code.

      114
      posts
  4. Community

    1. Gadget Factory

      Gadget Factory discussions. Have ideas to make Gadget Factory better? Having problems with the website? Let us know here.

      82
      posts
    2. Documentation

      Request any FPGA, VHDL, or Papilio related tutorials. We will do our best to write as many as we can.

      91
      posts
    3. FPGA Discussions

      Ask FPGA questions, share FPGA knowledge.

      766
      posts
    4. Community Projects

      Got an idea for a project, talk about it and even work on it with other members of the community.

      521
      posts
    5. Pipistrello

      Papilio on Steroids board developed by Saanlima Electronics.

      This is not produced by Gadget Factory but is a very interesting board we are happy to be associated with.

      http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello

      222
      posts
  5. Open Bench

    1. Open Bench Logic Sniffer at Dangerous Prototypes   (8,489 visits to this link)

      Discussions about the Open Bench Logic Sniffer on the Dangerous Prototypes Forum.

    2. OpenBench Logic Sniffer at Gadget Factory

      Discuss your OpenBench Logic Sniffer

      16
      posts
  • Recent Topics

  • New Downloads

  • Recent Posts

    • upper and lower case in Linux
      I have the same problem using Ubuntu with ISE 14.7 and a Papilio DUO. For example, when I create a blank project in DesignLab, edit the circuit with ISE and then generate a bit file, ISE creates a file called "Papilio_DUO_LX9.bit". However, when I try to load the file with DesignLab, it looks for and loads "papilio_duo_lx9.bit" (lower case), which is the original blank project. Cheers Jon
    • USB controller / wing
      Hmmm, Maybe it is time to experiment with a Papilio Nano format, where the Wing_B pins are removed and dedicated to high speed serial and the whole board is shrunk down to DIP size... Jack.
    • J1b on Duo tryout
      Here's what I think is going on, based on looking at the code in https://github.com/jamesbowman/swapforth/tree/master/j1b/verilog.  I think it indicates a read from some I/O device's registers.  That is, instead of reading/writing memory, the instruction reads some data provided by one of the peripheral devices. This is one of the common ways a computer design could allow access to I/O devices.  It looks like J1B uses a mixture of port-mapped and memory-mapped I/O (see https://en.wikipedia.org/wiki/Memory-mapped_I/O): as I look in xilinx-top.v I see that some memory accesses go to registers such as "uart_baud" too. Analysis in more detail: In j1.v: When "insn[6:4] == 5" then func_ior is asserted to 1. When that is true (along with some other things) then the output signal "io_rd" is asserted to 1. In xilinx-top.v: The signal io_rd is delayed one clock cycle (as io_rd_) and used, along with mem_addr (delayed as mem_addr_), to receive from the UART (see the signal uart_rd).  
    • CMT IP not available in ISE Webpack for Cortex6
      Thanks! I stuck with it and found the "clocking wizard" and saw how it had added the module to the symbol list for my project. One problem during simulation it complained during build about not being able to find the ports. I had named them in upper case in the wizard (CLK_IN1, CLK_OUT1), After checking the forum I tried naming them in lower case in the wizard and the project compiled and ran without trouble after that. As for the clock input, I downloaded the Eagle files and traced P94 (OSC_IN) to the output of the 32MHZ oscillator chip - realizing that should be the pin I map to the CLK_IN on my circuit in the user constraints file (.ucf)  Mike    
    • CMT IP not available in ISE Webpack for Cortex6
      The CMT (Clock Management Tile) is a block containing one PLL unit and two DCM units.  You can either instantiate a PLL or DCM unit directly in your code or use the "clocking wizard" to do it for you.  The clocking wizard is part of the Xilinx CORE generator (under FPGA Features and Design -> Clocking -> Clocking Wizard).  To learn more about the CMT, PLL and DCM check out this document: Spartan-6 FPGA Clocking Recources User Guide This guide will tell you how to directly instantiate a PLL or DCM unit (or any other library component) in your code: Xilinx Spartan-6 Libraries Guide for HDL Designs (page 99 and 213 for DCM and PLL). You should use the 32 MHz on-board oscillator as your clocking source, not the AVR SPI clock. If you let us know more about what you want to do (like I want to generate a 100 MHz clock for my circuit, how do I do that?) then we can give you more specific help. Edit: BTW, if you just want a clock input to your design but don't really care about the frequency then just use the 32 MHz on-board oscillator as your clock source, no need for a PLL or DCM.  You only need a PLL or DCM if you want to generated a different clock frequency (or multiple clocks with different clock frequencies).  For example, if your circuit has a VGA controller that needs to be clocked at 25 MHz then a DCM or a PLL will let you generate that clock from the 32 MHz input clock. Magnus